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OM -> OCM

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v0x3l 2020-03-01 15:11:22 -06:00
parent 831e12ad75
commit 472bc164d8
4 changed files with 58 additions and 50 deletions
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Zenith-latest-2020-02-29-20_30_18.iso → Zenith-latest-2020-03-01-15_08_21.iso
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28
src/Compiler/Asm.CC
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@ -228,33 +228,33 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
arg->imm_or_off_present = FALSE; //Zero displacement arg->imm_or_off_present = FALSE; //Zero displacement
if (arg->reg2 != REG_NONE || arg->scale != 1) if (arg->reg2 != REG_NONE || arg->scale != 1)
{ {//if reg or scale
res &= 0x0000FF0000; res &= ARGG_M|ARGG_RM; //0x0000FF0000;
goto mm_done; goto mm_done;
} }
if (arg->indirect) if (arg->indirect)
{ {
if (arg->imm_or_off_present) if (arg->imm_or_off_present)
res &= 0x00FFFF0000; res &= ARGG_RM|ARGG_M|ARGG_MN|ARGG_MOFFS;//0x00FFFF0000;
else else
res &= 0x000FFF0000; res &= ARGG_RM|ARGG_M|ARGG_MN;//0x000FFF0000;
} }
else else
{ {
if (arg->imm_or_off_present) if (arg->imm_or_off_present)
res &= 0x000F000FFE; res &= ARGG_MN|ARGG_IMM|ARGG_UIMM|ARGG_REL; //0x000F000FFE;
else else
res &= 0x3F0FFFF000; res &= ARGG_R|ARGG_RM|ARGG_M|ARGG_MN|ARGT_AL|ARGT_AX|ARGT_EAX|ARGT_RAX|ARGT_CL|ARGT_DX;//0x3F0FFFF000;
} }
if (arg->seg != REG_NONE) if (arg->seg != REG_NONE)
res&=0x00FFFF0000; res &= ARGG_RM|ARGG_M|ARGG_MN|ARGG_MOFFS;//0x00FFFF0000;
if (arg->reg1 == REG_NONE) if (arg->reg1 == REG_NONE)
{ {
if (arg->indirect) if (arg->indirect)
res &= 0x00FFFF0000; res &= ARGG_RM|ARGG_M|ARGG_MN|ARGG_MOFFS; //0x00FFFF0000;
else if (arg->num.i < 0) else if (arg->num.i < 0)
{ {
if (arg->num.i >= I8_MIN) if (arg->num.i >= I8_MIN)
@ -477,17 +477,17 @@ Bool ParseAsmInst(CCompCtrl *cc,CHashOpcode *tmpo,I64 argcount)
aotc->seg_size!=16 && tmpins->flags & IEF_OP_SIZE16) aotc->seg_size!=16 && tmpins->flags & IEF_OP_SIZE16)
cur.has_operand_prefix=TRUE; cur.has_operand_prefix=TRUE;
if (om==OM_IB) cur.imm.U8_count=1; if (om==OCM_IB) cur.imm.U8_count=1;
else if (om==OM_IW) cur.imm.U8_count=2; else if (om==OCM_IW) cur.imm.U8_count=2;
else if (om==OM_ID) cur.imm.U8_count=4; else if (om==OCM_ID) cur.imm.U8_count=4;
if (om==OM_CB) { if (om==OCM_CB) {
cur.imm.U8_count=1; cur.imm.U8_count=1;
cur.imm.imm_flag=FALSE; cur.imm.imm_flag=FALSE;
} else if (om==OM_CW) { } else if (om==OCM_CW) {
cur.imm.U8_count=2; cur.imm.U8_count=2;
cur.imm.imm_flag=FALSE; cur.imm.imm_flag=FALSE;
} else if (om==OM_CD) { } else if (om==OCM_CD) {
cur.imm.U8_count=4; cur.imm.U8_count=4;
cur.imm.imm_flag=FALSE; cur.imm.imm_flag=FALSE;
} }

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src/Home/PersonalMenu.DD
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80
src/Kernel/KernelA.HH
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@ -1887,14 +1887,14 @@ class CInst
}; };
//x86 opcodes //x86 opcodes
#define OC_OP_SIZE_PREFIX 0x66 #define OC_OP_SIZE_PREFIX 0x66
#define OC_ADDR_SIZE_PREFIX 0x67 #define OC_ADDR_SIZE_PREFIX 0x67
#define OC_LOCK_PREFIX 0xF0 #define OC_LOCK_PREFIX 0xF0
#define OC_NOP 0x90 #define OC_NOP 0x90
#define OC_BPT 0xCC #define OC_BPT 0xCC
#define OC_CALL 0xE8 #define OC_CALL 0xE8
#define OC_JMP_REL8 0xEB #define OC_JMP_REL8 0xEB
#define OC_NOP2 (OC_NOP<<8+OC_OP_SIZE_PREFIX) #define OC_NOP2 (OC_NOP<<8+OC_OP_SIZE_PREFIX)
#define PUSH_C_REGS PUSH RAX PUSH RCX PUSH RDX PUSH RBX PUSH R8 PUSH R9 #define PUSH_C_REGS PUSH RAX PUSH RCX PUSH RDX PUSH RBX PUSH R8 PUSH R9
#define POP_C_REGS POP R9 POP R8 POP RBX POP RDX POP RCX POP RAX #define POP_C_REGS POP R9 POP R8 POP RBX POP RDX POP RCX POP RAX
@ -1904,31 +1904,31 @@ PUSH RDI PUSH R8 PUSH R9 PUSH R10 PUSH R11 PUSH R12 PUSH R13 PUSH R14 PUSH R15
#define POP_REGS POP R15 POP R14 POP R13 POP R12 POP R11 POP R10 POP R9 \ #define POP_REGS POP R15 POP R14 POP R13 POP R12 POP R11 POP R10 POP R9 \
POP R8 POP RDI POP RSI POP RBP POP RBX POP RDX POP RCX POP RAX POP R8 POP RDI POP RSI POP RBP POP RBX POP RDX POP RCX POP RAX
#define REG_RAX 0 #define REG_RAX 0
#define REG_RCX 1 #define REG_RCX 1
#define REG_RDX 2 #define REG_RDX 2
#define REG_RBX 3 #define REG_RBX 3
#define REG_RSP 4 #define REG_RSP 4
#define REG_RBP 5 #define REG_RBP 5
#define REG_RSI 6 #define REG_RSI 6
#define REG_RDI 7 #define REG_RDI 7
#define REG_R8 8 #define REG_R8 8
#define REG_REGS_NUM 16 #define REG_REGS_NUM 16
#define REG_RIP 16 //Used by compiler, not really it's num #define REG_RIP 16 //Used by compiler, not really it's num
//Be careful: RBPu8, RSPu8, RSIu8, RDIu8 are 20-24 //Be careful: RBPu8, RSPu8, RSIu8, RDIu8 are 20-24
#define REG_NONE 32 //noreg flag sets it to this #define REG_NONE 32 //noreg flag sets it to this
#define REG_ALLOC 33 //reg flag sets it to this #define REG_ALLOC 33 //reg flag sets it to this
#define REG_UNDEF I8_MIN #define REG_UNDEF I8_MIN
#define REGG_CLOBBERED 0x013F //RAX,RCX,RDX,RBX,R8 #define REGG_CLOBBERED 0x013F //RAX,RCX,RDX,RBX,R8
#define REGG_SAVED 0x0030 //RBP,RSP #define REGG_SAVED 0x0030 //RBP,RSP
#define REGG_STACK_TMP 0x0200 //R9 #define REGG_STACK_TMP 0x0200 //R9
#define REGG_LOCAL_VARS 0xCCC0 //RSI,RDI,R10,R11,R14,R15 #define REGG_LOCAL_VARS 0xCCC0 //RSI,RDI,R10,R11,R14,R15
#define REGG_LOCAL_NON_PTR_VARS 0x3000 //R12,R13 #define REGG_LOCAL_NON_PTR_VARS 0x3000 //R12,R13
#define AOT_BIN_BLK_BITS 16 #define AOT_BIN_BLK_BITS 16
#define AOT_BIN_BLK_SIZE (1<<AOT_BIN_BLK_BITS) #define AOT_BIN_BLK_SIZE (1<<AOT_BIN_BLK_BITS)
class CAOTBinBlk class CAOTBinBlk
{ {
@ -2000,14 +2000,14 @@ class CAsmUnresolvedRef
}; };
//Opcode Modifier //Opcode Modifier
#define OM_NO 0 #define OCM_NO 0
#define OM_CB 1 #define OCM_CB 1
#define OM_CW 2 #define OCM_CW 2
#define OM_CD 3 #define OCM_CD 3
#define OM_CP 4 #define OCM_CP 4
#define OM_IB 5 #define OCM_IB 5
#define OM_IW 6 #define OCM_IW 6
#define OM_ID 7 #define OCM_ID 7
#define ARGt_NONE 0 #define ARGt_NONE 0
#define ARGt_REL8 1 #define ARGt_REL8 1
@ -2017,6 +2017,7 @@ class CAsmUnresolvedRef
#define ARGT_REL8 (1<<ARGt_REL8) #define ARGT_REL8 (1<<ARGt_REL8)
#define ARGT_REL16 (1<<ARGt_REL16) #define ARGT_REL16 (1<<ARGt_REL16)
#define ARGT_REL32 (1<<ARGt_REL32) #define ARGT_REL32 (1<<ARGt_REL32)
#define ARGG_REL (ARGT_REL8|ARGT_REL16|ARGT_REL32)
#define ARGt_IMM8 4 #define ARGt_IMM8 4
#define ARGt_IMM16 5 #define ARGt_IMM16 5
@ -2026,6 +2027,7 @@ class CAsmUnresolvedRef
#define ARGT_IMM16 (1<<ARGt_IMM16) #define ARGT_IMM16 (1<<ARGt_IMM16)
#define ARGT_IMM32 (1<<ARGt_IMM32) #define ARGT_IMM32 (1<<ARGt_IMM32)
#define ARGT_IMM64 (1<<ARGt_IMM64) #define ARGT_IMM64 (1<<ARGt_IMM64)
#define ARGG_IMM (ARGT_IMM8|ARGT_IMM16|ARGT_IMM32|ARGT_IMM64)
#define ARGt_UIMM8 8 #define ARGt_UIMM8 8
#define ARGt_UIMM16 9 #define ARGt_UIMM16 9
@ -2035,6 +2037,7 @@ class CAsmUnresolvedRef
#define ARGT_UIMM16 (1<<ARGt_UIMM16) #define ARGT_UIMM16 (1<<ARGt_UIMM16)
#define ARGT_UIMM32 (1<<ARGt_UIMM32) #define ARGT_UIMM32 (1<<ARGt_UIMM32)
#define ARGT_UIMM64 (1<<ARGt_UIMM64) #define ARGT_UIMM64 (1<<ARGt_UIMM64)
#define ARGG_UIMM (ARGT_UIMM8|ARGT_UIMM16|ARGT_UIMM32|ARGT_UIMM64)
#define ARGt_R8 12 #define ARGt_R8 12
#define ARGt_R16 13 #define ARGt_R16 13
@ -2044,6 +2047,7 @@ class CAsmUnresolvedRef
#define ARGT_R16 (1<<ARGt_R16) #define ARGT_R16 (1<<ARGt_R16)
#define ARGT_R32 (1<<ARGt_R32) #define ARGT_R32 (1<<ARGt_R32)
#define ARGT_R64 (1<<ARGt_R64) #define ARGT_R64 (1<<ARGt_R64)
$ER$#define ARGG_R (ARGT_R8|ARGT_R16|ARGT_R32|ARGT_R64)
#define ARGt_RM8 16 #define ARGt_RM8 16
#define ARGt_RM16 17 #define ARGt_RM16 17
@ -2053,6 +2057,7 @@ class CAsmUnresolvedRef
#define ARGT_RM16 (1<<ARGt_RM16) #define ARGT_RM16 (1<<ARGt_RM16)
#define ARGT_RM32 (1<<ARGt_RM32) #define ARGT_RM32 (1<<ARGt_RM32)
#define ARGT_RM64 (1<<ARGt_RM64) #define ARGT_RM64 (1<<ARGt_RM64)
#define ARGG_RM (ARGT_RM8|ARGT_RM16|ARGT_RM32|ARGT_RM64)
#define ARGt_M8 20 #define ARGt_M8 20
#define ARGt_M16 21 #define ARGt_M16 21
@ -2062,6 +2067,7 @@ class CAsmUnresolvedRef
#define ARGT_M16 (1<<ARGt_M16) #define ARGT_M16 (1<<ARGt_M16)
#define ARGT_M32 (1<<ARGt_M32) #define ARGT_M32 (1<<ARGt_M32)
#define ARGT_M64 (1<<ARGt_M64) #define ARGT_M64 (1<<ARGt_M64)
#define ARGG_M (ARGT_M8|ARGT_M16|ARGT_M32|ARGT_M64)
#define ARGt_M1632 24 // Not implemented #define ARGt_M1632 24 // Not implemented
#define ARGt_M16N32 25 // Not implemented #define ARGt_M16N32 25 // Not implemented
@ -2071,6 +2077,7 @@ class CAsmUnresolvedRef
#define ARGT_M16N32 (1<<ARGt_M16N32) #define ARGT_M16N32 (1<<ARGt_M16N32)
#define ARGT_M16N16 (1<<ARGt_M16N16) #define ARGT_M16N16 (1<<ARGt_M16N16)
#define ARGT_M32N32 (1<<ARGt_M32N32) #define ARGT_M32N32 (1<<ARGt_M32N32)
#define ARGG_MN (ARGT_M1632|ARGT_M16N32|ARGT_M16N16|ARGT_M32N32)
#define ARGt_MOFFS8 28 #define ARGt_MOFFS8 28
#define ARGt_MOFFS16 29 #define ARGt_MOFFS16 29
@ -2109,6 +2116,7 @@ class CAsmUnresolvedRef
#define ARGT_FS (1<<ARGt_FS) #define ARGT_FS (1<<ARGt_FS)
#define ARGT_GS (1<<ARGt_GS) #define ARGT_GS (1<<ARGt_GS)
#define ARGT_CS (1<<ARGt_CS) #define ARGT_CS (1<<ARGt_CS)
#define ARGG_SREG (ARGT_SREG|ARGT_SS|ARGT_DS|ARGT_ES|ARGT_FS|ARGT_GS|ARGT_CS)
#define ARGt_ST0 46 #define ARGt_ST0 46
#define ARGt_STI 47 #define ARGt_STI 47