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arg size mask defines

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This commit is contained in:
v0x3l 2020-03-03 21:30:53 -06:00
parent c957c3e723
commit c3c6a8c6ee
8 changed files with 31 additions and 40 deletions
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BIN
Zenith-latest-2020-03-03-18_03_35.iso → Zenith-latest-2020-03-03-21_30_17.iso
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37
src/Compiler/Asm.CC
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@ -223,8 +223,7 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
if (aotc->seg_size == 64)
res &= ~ARGG_MOFFS;
if (arg->reg1 != REG_NONE && arg->imm_or_off_present && !arg->num.i &&
!arg->num.global_asm_undef_hash && !arg->num.local_asm_undef_hash)
if (arg->reg1 != REG_NONE && arg->imm_or_off_present && !arg->num.i && !arg->num.global_asm_undef_hash && !arg->num.local_asm_undef_hash)
arg->imm_or_off_present = FALSE; //Zero displacement
if (arg->reg2 != REG_NONE || arg->scale != 1)
@ -245,7 +244,7 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
if (arg->imm_or_off_present)
res &= ARGG_MN | ARGG_IMM | ARGG_UIMM | ARGG_REL;
else
res &= ARGG_R | ARGG_RM | ARGG_M | ARGG_MN | ARGT_AL | ARGT_AX | ARGT_EAX | ARGT_RAX | ARGT_CL | ARGT_DX;
res &= ARGG_R | ARGG_RM | ARGG_M | ARGG_MN | ARGG_AXCLDX;
}
if (arg->seg != REG_NONE)
@ -258,45 +257,45 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
else if (arg->num.i < 0)
{
if (arg->num.i >= I8_MIN)
res &= ARGG_REL | ARGG_IMM;//|ARGT_UIMM64; //0x8FE;
res &= ARGG_REL | ARGG_IMM;
else if (arg->num.i >= I16_MIN)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16;///|ARGT_UIMM64;//0x8EE;
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16;
else if (arg->num.i >= I32_MIN)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32;//|ARGT_UIMM64;//0x8CE;
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32;
else
res &= ARGG_REL | ARGT_IMM64;//|ARGT_UIMM64;//0x88E;
res &= ARGG_REL | ARGT_IMM64;
}
else
{
if (arg->num.i <= I8_MAX)
res &= ARGG_REL|ARGG_IMM|ARGG_UIMM;//0xFFE;
res &= ARGG_REL | ARGG_IMM | ARGG_UIMM;
else if (arg->num.i <= U8_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGG_UIMM;//0xFEE;
res &= ARGG_REL | ARGG_IMM & ~ARGT_IMM8 | ARGG_UIMM;
else if (arg->num.i <= I16_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xEEE;
res &= ARGG_REL | ARGG_IMM & ~ARGT_IMM8 | ARGG_UIMM & ~ARGT_UIMM8;
else if (arg->num.i <= U16_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xECE;
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGG_UIMM & ~ARGT_UIMM8;
else if (arg->num.i <= I32_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32;//0xCCE;
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32;
else if (arg->num.i <= U32_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64 | ARGT_UIMM32;//0xC8E;
res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64 | ARGT_UIMM32;
else
res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64;//0x88E;
res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64;
}
}
else
{
res &= ARGG_R | ARGG_RM | ARGG_M | ARGT_AL | ARGT_AX | ARGT_EAX | ARGT_RAX | ARGT_CL | ARGT_DX;//0x3F00FFF000;
res &= ARGG_R | ARGG_RM | ARGG_M | ARGG_AXCLDX;
if (!arg->indirect) //M8-M64
res &= ~ARGG_M;
}
switch (arg->reg1)
{
case REG_RAX: res &= ~(ARGT_CL|ARGT_DX); break;//0x3000000000;
case REG_RCX: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_DX); break;//~0x2F00000000
case REG_RDX: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_CL); break;//~0x1F00000000
default: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_CL|ARGT_DX);//~0x3F00000000
case REG_RAX: res &= ~(ARGT_CL | ARGT_DX); break;
case REG_RCX: res &= ~(ARGG_AXCLDX & ~ARGT_CL); break;
case REG_RDX: res &= ~(ARGG_AXCLDX & ~ARGT_DX); break;
default: res &= ~(ARGG_AXCLDX);
}
mm_done:
return res;

12
src/Compiler/AsmInit.CC
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@ -69,11 +69,11 @@ U0 AsmHashLoad()
CInst *tmpins;
CHashClass *tmpc;
comp.size_arg_mask[0] = 0x3FF0FFFFFE;
comp.size_arg_mask[1] = 0x1110111112;
comp.size_arg_mask[2] = 0x2220222224;
comp.size_arg_mask[4] = 0x0440444448;
comp.size_arg_mask[8] = ARGG_SIZE_8;//0x20000880888880;
comp.size_arg_mask[0] = ARGG_SIZE_0;
comp.size_arg_mask[1] = ARGG_SIZE_1;
comp.size_arg_mask[2] = ARGG_SIZE_2;
comp.size_arg_mask[4] = ARGG_SIZE_4;
comp.size_arg_mask[8] = ARGG_SIZE_8;
comp.size_arg_mask[16] = ARGG_SIZE_16;
comp.asm_hash = HashTableNew(1024);
@ -87,7 +87,7 @@ U0 AsmHashLoad()
{
if (cc->token != TK_IDENT)
LexExcept(cc, "Expecting identifier at ");
i = ListMatch(cc->cur_str, "NONE\0R8\0R16\0R32\0R64\0SEG\0FSTACK\0XMM\0OPCODE\0KEYWORD\0ASM_KEYWORD\0");
i = ListMatch(cc->cur_str, "NONE\0R8\0R16\0R32\0R64\0SEG\0FSTACK\0XMM\0OPCODE\0KEYWORD\0ASM_KEYWORD");
if (i <= 0)
LexExcept(cc,"Unknown Statement");
Lex(cc); //skip keyword

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src/Doc/HelpIndex.DD
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2
src/Home/K.CC
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@ -1,4 +1,4 @@
In("CC\n\n1\n\n5\n\n\n");
In("CC\n\n1\n\n6\n\n\n");
BootHDIns;
"\n\nSuccessful? ";
if(YorN)

10
src/Home/Registry.CC
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@ -1,10 +0,0 @@
$TR,"Zenith"$
$ID,2$$TR,"SysMessageFlags"$
$ID,2$sys_message_flags[0]=0;
$ID,-2$$TR,"SysRegVer"$
$ID,2$registry_version=1.000;
$ID,-2$$ID,-2$$TR,"Once"$
$ID,2$$TR,"Zenith"$
$ID,2$$ID,-2$$TR,"User"$
$ID,2$$ID,-2$$ID,-2$$TR,"AutoComplete"$
$ID,2$ac.col = TEXT_COLS-30;ac.row = TEXT_ROWS/5+4;$ID,-2$

8
src/Kernel/KernelA.HH
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@ -2047,7 +2047,7 @@ class CAsmUnresolvedRef
#define ARGT_R16 (1<<ARGt_R16)
#define ARGT_R32 (1<<ARGt_R32)
#define ARGT_R64 (1<<ARGt_R64)
$ER$#define ARGG_R (ARGT_R8|ARGT_R16|ARGT_R32|ARGT_R64)
#define ARGG_R (ARGT_R8|ARGT_R16|ARGT_R32|ARGT_R64)
#define ARGt_RM8 16
#define ARGt_RM16 17
@ -2101,6 +2101,7 @@ $ER$#define ARGG_R (ARGT_R8|ARGT_R16|ARGT_R32|ARGT_R64)
#define ARGT_RAX (1<<ARGt_RAX)
#define ARGT_CL (1<<ARGt_CL)
#define ARGT_DX (1<<ARGt_DX)
#define ARGG_AXCLDX (ARGT_AL|ARGT_AX|ARGT_EAX|ARGT_RAX|ARGT_CL|ARGT_DX)
#define ARGt_SREG 39
#define ARGt_SS 40
@ -2140,8 +2141,9 @@ $ER$#define ARGG_R (ARGT_R8|ARGT_R16|ARGT_R32|ARGT_R64)
#define ARGT_XMM128 (1<<ARGt_XMM128)
#define ARGT_M128 (1<<55)
#define ARGG_SIZE_1 (1)
#define ARGG_SIZE_2 (1)
#define ARGG_SIZE_0 (ARGG_REL|ARGG_IMM|ARGG_UIMM|ARGG_R|ARGG_RM|ARGG_M|ARGG_MOFFS|ARGG_AXCLDX)
#define ARGG_SIZE_1 (ARGT_REL8|ARGT_IMM8|ARGT_UIMM8|ARGT_R8|ARGT_RM8|ARGT_M8|ARGT_MOFFS8|ARGT_AL|ARGT_CL)
#define ARGG_SIZE_2 (ARGT_REL16|ARGT_IMM16|ARGT_UIMM16|ARGT_R16|ARGT_RM16|ARGT_M16|ARGT_MOFFS16|ARGT_AX|ARGT_DX)
#define ARGG_SIZE_4 (ARGT_REL32|ARGT_IMM32|ARGT_UIMM32|ARGT_R32|ARGT_RM32|ARGT_M32|ARGT_MOFFS32|ARGT_EAX)
#define ARGG_SIZE_8 (ARGT_IMM64|ARGT_UIMM64|ARGT_R64|ARGT_RM64|ARGT_M64|ARGT_MOFFS64|ARGT_RAX|ARGT_XMM64)
#define ARGG_SIZE_16 (ARGT_XMM|ARGT_XMM0|ARGT_XMM128|ARGT_M128)

2
src/Once.CC
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@ -52,4 +52,4 @@ U0 Tmp()
}
}
Tmp;
PaletteSetGruvboxLight;
PaletteSetDark;