diff --git a/Zenith-latest-2020-03-02-17_34_27.iso b/Zenith-latest-2020-03-03-18_03_35.iso
similarity index 99%
rename from Zenith-latest-2020-03-02-17_34_27.iso
rename to Zenith-latest-2020-03-03-18_03_35.iso
index e25ebc85..280a7657 100755
Binary files a/Zenith-latest-2020-03-02-17_34_27.iso and b/Zenith-latest-2020-03-03-18_03_35.iso differ
diff --git a/src/Compiler/Asm.CC b/src/Compiler/Asm.CC
index 9c881295..d9eb3d81 100755
--- a/src/Compiler/Asm.CC
+++ b/src/Compiler/Asm.CC
@@ -273,30 +273,30 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
 			else if (arg->num.i <= U8_MAX)
 				res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGG_UIMM;//0xFEE;
 			else if (arg->num.i <= I16_MAX)
-				res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32  |ARGT_IMM16 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xEEE;
+				res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xEEE;
 			else if (arg->num.i <= U16_MAX)
 				res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xECE;
 			else if (arg->num.i <= I32_MAX)
-				res &= 0xCCE;
+				res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32;//0xCCE;
 			else if (arg->num.i <= U32_MAX)
-				res &= 0xC8E;
+				res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64 | ARGT_UIMM32;//0xC8E;
 			else
-				res &= 0x88E;
+				res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64;//0x88E;
 		}
 	}
 	else
 	{
-		res &= 0x3F00FFF000;
+		res &= ARGG_R | ARGG_RM | ARGG_M | ARGT_AL | ARGT_AX | ARGT_EAX | ARGT_RAX | ARGT_CL | ARGT_DX;//0x3F00FFF000;
 		if (!arg->indirect) //M8-M64
-			res &= 0xFFFF0FFFFF;
+			res &= ~ARGG_M;
 	}
 
 	switch (arg->reg1)
 	{
-		case REG_RAX: res&=~0x3000000000; break;
-		case REG_RCX: res&=~0x2F00000000; break;
-		case REG_RDX: res&=~0x1F00000000; break;
-		default:      res&=~0x3F00000000;
+		case REG_RAX: res &= ~(ARGT_CL|ARGT_DX); break;//0x3000000000;
+		case REG_RCX: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_DX); break;//~0x2F00000000
+		case REG_RDX: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_CL); break;//~0x1F00000000
+		default:      res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_CL|ARGT_DX);//~0x3F00000000
 	}
 mm_done:
 	return res;
diff --git a/src/Home/PCNet.CC b/src/Home/PCNet.CC
index 2752ab5a..ed4842a5 100755
--- a/src/Home/PCNet.CC
+++ b/src/Home/PCNet.CC
@@ -117,18 +117,13 @@ CPCIDev* PCNetPCIDevFind()
 }
 
 U32 PCNetGetIOBase()
-{/* Return memory IO base address
-	of PCNet card. Bits 0-4 are not
-	for the IO base, so an AND with
-	~0x1F ignores those bits. */
+{//Return memory IO base address of PCNet card. Bits 0-4 are not for the IO base, so an AND with ~0x1F ignores those bits.
 	U32 io_base = pcnet.pci->base[0] & ~0x1F;
 	return io_base;
 }
 
 U0 PCNetReset()
-{/* Reads the 32- and 16-bit RESET registers,
-	which, regardless of which mode the card is in,
-	will reset it back to 16-bit mode. */
+{//Reads the 32-/16-bit RESET registers, which, regardless of which mode the card is in, will reset it back to 16-bit mode.
 	InU32(PCNetGetIOBase() + PCNET_DW_RESET);
 	InU16(PCNetGetIOBase() + PCNET_WD_RESET);
 	Sleep(1); // OSDev says minimum 1 ęS
@@ -136,9 +131,7 @@ U0 PCNetReset()
 
 U0 PCNetEnter32BitMode()
 {/* AMD PCNet datasheet p. 1-930
-	Summary: A 32-bit write (while in 16-bit mode)
-	to RDP  will cause 16-bit mode exit
-	and immediate enter into 32-bit mode. */
+	Summary: A 32-bit write (while in 16-bit mode) to RDP  will cause 16-bit mode exit and immediate enter into 32-bit mode.*/
 	OutU32(PCNetGetIOBase() + PCNET_DW_RDP, 0);
 
 }
@@ -535,9 +528,6 @@ U0 PCNetInit()
 	"pcnet->tx_de_buffer: %X\n",pcnet.tx_de_buffer;
 	"pcnet->rx_de_buffer_phys: %X\n",pcnet.rx_de_buffer_phys;
 	"pcnet->rx_de_buffer_phys: %X\n",pcnet.tx_de_buffer_phys;
-
-
 }
 
-
 PCNetInit();