mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2025-06-07 08:14:48 +00:00
Added comments to PICInit, fixed some of KernelA.
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@ -1,4 +1,9 @@
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$WW,1$$FG,5$$TX+CX,"ChangeLog"$$FG$
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$IV,1$----04/13/20 13:48:15----$IV,0$
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* Added $LK,"PIC_INIT",A="MN:PIC_INIT"$ and comments to $LK,"IntPICInit",A="MN:IntPICInit"$().
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* $LK,"R",A="MN:R"$("IntsInit", "$LK,"IntPICInit",A="MN:IntPICInit"$");
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* $LK,"R",A="MN:R"$("LAPIC_ARIBITRATION_PRIORITY", "$LK,"LAPIC_ARBITRATION_PRIORITY",A="MN:LAPIC_ARBITRATION_PRIORITY"$");
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$IV,1$----04/12/20 17:06:38----$IV,0$
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* Added $LK,"CIDTEntry",A="MN:CIDTEntry"$ and rewrote $LK,"IntEntryGet",A="MN:IntEntryGet"$() and $LK,"IntEntrySet",A="MN:IntEntrySet"$(). $LK,"dev",A="MN:CDevGlobals"$.idt is now $LK,"allocated",A="FF:::/Kernel/KInterrupts.CC,CAllocAligned"$ on an 8-byte boundary as per Intel SDM recommendation.
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* Updated $LK,"OS version",A="MN:sys_os_version"$.
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@ -4,7 +4,7 @@ If a feature cannot be made to work correctly and consistently, professional com
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The PCI bus interface is what modern hardware uses. Before PCI, life was simple and devices used I/O ports. After studying $LK,"PCI Interrupts",A="FI:::/Demo/Lectures/PCIInterrupts.CC"$ and attempting to do a HDAudio driver, I came to realize that modern PCI devices require ten times more code and I cannot even come close to making them work on everyone's machine because with PCI devices there are several models to worry about, unlike with the older ISA bus devices which can be done with one driver.
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Currently, I have no PCI drivers. My drivers use I/O ports and operate in ISA bus mode. At this point, I only have one driver for each type of device and it is delightfully simple that way. I have one $LK,"keyboard",A="FI:::/Kernel/SerialDev/Keyboard.CC"$ driver, one $LK,"mouse",A="FI:::/Kernel/SerialDev/Mouse.CC"$ driver, one $LK,"ATA hard drive",A="FI:::/Kernel/BlkDev/DiskATA.CC"$ driver, one $LK,"ATAPI CD/DVD",A="FI:::/Kernel/BlkDev/DiskATA.CC"$ driver, one $LK,"VGA 640x480 16 color",A="FI:::/Zenith/Gr/GrScreen.CC"$ video driver and one $LK,"PC Speaker",A="MN:Sound"$ driver. I use the $LK,"PIT timer",A="MN:TimerInit"$ and $LK,"PIC Interrupt Controller",A="MN:IntsInit"$. I use IRQ0 for timer, IRQ1 for keyboard, and IRQ12 for mouse. If IRQ12 is not firing, I am able to poll the mouse.
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Currently, I have no PCI drivers. My drivers use I/O ports and operate in ISA bus mode. At this point, I only have one driver for each type of device and it is delightfully simple that way. I have one $LK,"keyboard",A="FI:::/Kernel/SerialDev/Keyboard.CC"$ driver, one $LK,"mouse",A="FI:::/Kernel/SerialDev/Mouse.CC"$ driver, one $LK,"ATA hard drive",A="FI:::/Kernel/BlkDev/DiskATA.CC"$ driver, one $LK,"ATAPI CD/DVD",A="FI:::/Kernel/BlkDev/DiskATA.CC"$ driver, one $LK,"VGA 640x480 16 color",A="FI:::/Zenith/Gr/GrScreen.CC"$ video driver and one $LK,"PC Speaker",A="MN:Sound"$ driver. I use the $LK,"PIT timer",A="MN:TimerInit"$ and $LK,"PIC Interrupt Controller",A="MN:IntPICInit"$. I use IRQ0 for timer, IRQ1 for keyboard, and IRQ12 for mouse. If IRQ12 is not firing, I am able to poll the mouse.
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In the CPU department, I have state of the art 64-bit $LK,"long mode",A="FI:::/Kernel/KStart64.CC"$ with $LK,"multicore",A="FI:::/Kernel/MultiProc.CC"$ support. I use the $LK,"APIC",A="MN:MPAPICInit"$ and start-up $LK,"multicore",A="MN:Core0StartMP"$ operation.
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@ -1,32 +1,33 @@
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//Compiler initializes globals in AOT bin modules to zero.
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//$LK,"Globals Set to Zero Here",A="FF:::/Compiler/ParseStatement.CC,Init AOT global to zero"$.
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CJob sys_macro_head;
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CTask *sys_macro_task;
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CDoc *sys_clip_doc;
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CJob sys_macro_head;
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CTask *sys_macro_task;
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CDoc *sys_clip_doc;
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CTask *zenith_task;
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I64 sys_num_spawned_tasks;
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CTask *zenith_task;
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I64 sys_num_spawned_tasks;
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CTask *sys_winmgr_task,*sys_task_being_screen_updated;
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U8 *rev_bits_table; //Table with U8 bits reversed
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CDate local_time_offset;
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F64 *pow10_I64,
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sys_os_version=1.12;
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CTask *sys_winmgr_task,
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*sys_task_being_screen_updated;
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U8 *rev_bits_table; //Table with U8 bits reversed
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CDate local_time_offset;
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F64 *pow10_I64,
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sys_os_version = 1.12;
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CAutoCompleteDictGlobals acd;
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CAutoCompleteGlobals ac;
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CBlkDevGlobals blkdev;
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CCountsGlobals counts={1,0,2676302000,2676302,2676302000,FALSE};
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CDebugGlobals debug;
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CDevGlobals dev;
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CGridGlobals mouse_grid; //See $LK,"::/Demo/Graphics/Grid.CC"$.
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CMouseStateGlobals mouse,mouse_last;
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CKbdStateGlobals kbd;
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CKeyDevGlobals keydev;
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CMouseHardStateGlobals mouse_hard,mouse_hard_last;
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CScreenCastGlobals screencast;
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CTextGlobals text;
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CAutoCompleteGlobals ac;
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CBlkDevGlobals blkdev;
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CCountsGlobals counts={1,0,2676302000,2676302,2676302000,FALSE};
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CDebugGlobals debug;
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CDevGlobals dev;
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CGridGlobals mouse_grid; //See $LK,"::/Demo/Graphics/Grid.CC"$.
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CMouseStateGlobals mouse,mouse_last;
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CKbdStateGlobals kbd;
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CKeyDevGlobals keydev;
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CMouseHardStateGlobals mouse_hard,mouse_hard_last;
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CScreenCastGlobals screencast;
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CTextGlobals text;
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U8 *(*fp_getstr2)(I64 flags=0);
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U0 (*fp_update_ctrls)(CTask *task);
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@ -125,16 +125,16 @@ U8 *IntEntrySet(I64 irq, U0 (*fp_new_handler)(), I64 type=IDTET_IRQ)
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return old_handler;
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}
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U0 IntsInit()
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U0 IntPICInit()
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{//Init 8259
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OutU8(PIC_1, 0x11); //IW1
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OutU8(PIC_2, 0x11); //IW1
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OutU8(PIC_1_DATA, 0x20); //IW2
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OutU8(PIC_2_DATA, 0x28); //IW2
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OutU8(PIC_1_DATA, 0x04); //IW3
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OutU8(PIC_2_DATA, 0x02); //IW3
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OutU8(PIC_1_DATA, 0x0D); //IW4
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OutU8(PIC_2_DATA, 0x09); //IW4
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OutU8(PIC_1, PIC_INIT); //IW (Initialization Word) 1
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OutU8(PIC_2, PIC_INIT); //IW1
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OutU8(PIC_1_DATA, 0x20); //IW2 Moving IRQ base from 0 -> 32 (beyond Intel reserved faults)
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OutU8(PIC_2_DATA, 0x28); //IW2 Moving IRQ base from 8 -> 40
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OutU8(PIC_1_DATA, 0x04); //IW3 Telling PIC_1 PIC_2 exists.
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OutU8(PIC_2_DATA, 0x02); //IW3 Telling PIC_2 its cascade identity.
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OutU8(PIC_1_DATA, 0x0D); //IW4 8086 Mode, Buffered Mode (Master PIC)
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OutU8(PIC_2_DATA, 0x09); //IW4 8086 Mode, Buffered Mode (Slave PIC)
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OutU8(PIC_1_DATA, 0xFA); //Mask all but IRQ0 (timer) and IRQ2 Cascade.
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OutU8(PIC_2_DATA, 0xFF);
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}
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@ -161,7 +161,7 @@ U0 KMain()
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if (MemBIOSTotal < ToI64 (0.95*MEM_MIN_MEG*0x100000) )
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RawPrint(4000,"!!! Requires $TX,"256Meg",D="DD_MEM_MIN_MEG"$ of RAM Memory !!!");
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IntsInit;
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IntPICInit;
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"Enable IRQs\n";
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RFlagsSet(RFLAGG_NORMAL);
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Busy(2000);
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@ -16,228 +16,240 @@ extern class CIntermediateCode;
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extern class CJobCtrl;
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extern class CTask;
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#define NULL 0
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#define TRUE 1
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#define FALSE 0
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#define ON 1
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#define OFF 0
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#define NONE 0 //for use in default arguments
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#define I8_MIN (-0x80)
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#define I8_MAX 0x7F
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#define U8_MIN 0
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#define U8_MAX 0xFF
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#define I16_MIN (-0x8000)
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#define I16_MAX 0x7FFF
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#define U16_MIN 0
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#define U16_MAX 0xFFFF
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#define I32_MIN (-0x80000000)
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#define I32_MAX 0x7FFFFFFF
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#define U32_MIN 0
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#define U32_MAX 0xFFFFFFFF
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#define I64_MIN (-0x8000000000000000)
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#define I64_MAX 0x7FFFFFFFFFFFFFFF
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#define U64_MIN 0
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#define U64_MAX 0xFFFFFFFFFFFFFFFF
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#define NULL 0
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#define TRUE 1
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#define FALSE 0
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#define ON 1
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#define OFF 0
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#define NONE 0 //for use in default arguments
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#define I8_MIN (-0x80)
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#define I8_MAX 0x7F
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#define U8_MIN 0
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#define U8_MAX 0xFF
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#define I16_MIN (-0x8000)
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#define I16_MAX 0x7FFF
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#define U16_MIN 0
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#define U16_MAX 0xFFFF
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#define I32_MIN (-0x80000000)
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#define I32_MAX 0x7FFFFFFF
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#define U32_MIN 0
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#define U32_MAX 0xFFFFFFFF
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#define I64_MIN (-0x8000000000000000)
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#define I64_MAX 0x7FFFFFFFFFFFFFFF
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#define U64_MIN 0
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#define U64_MAX 0xFFFFFFFFFFFFFFFF
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#define INVALID_PTR I64_MAX
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#define STR_LEN 144
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#define STR_LEN 144
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//(Int to F64 conversion is signed)
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//Turn off 80-bit float constants with $LK,"OPTf_NO_BUILTIN_CONST",A="MN:OPTf_NO_BUILTIN_CONST"$.
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#define U64_F64_MAX (0x43F0000000000000(F64))
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#define F64_MAX (0x7FEFFFFFFFFFFFFF(F64))
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#define F64_MIN (0xFFEFFFFFFFFFFFFF(F64))
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#define inf (0x7FF0000000000000(F64))
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#define ì (0x7FF0000000000000(F64))
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#define pi (0x400921FB54442D18(F64))
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#define ã (0x400921FB54442D18(F64))
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#define exp_1 (0x4005BF0A8B145769(F64)) //The number "e"
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#define log2_10 (0x400A934F0979A371(F64))
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#define log2_e (0x3FF71547652B82FE(F64))
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#define log10_2 (0x3FD34413509F79FF(F64))
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#define loge_2 (0x3FE62E42FEFA39EF(F64))
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#define sqrt2 (0x3FF6A09E667F3BCD(F64))
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#define eps (0x3CB0000000000000(F64))
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#define F64_MAX (0x7FEFFFFFFFFFFFFF(F64))
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#define F64_MIN (0xFFEFFFFFFFFFFFFF(F64))
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#define inf (0x7FF0000000000000(F64))
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#define ì (0x7FF0000000000000(F64))
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#define pi (0x400921FB54442D18(F64))
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#define ã (0x400921FB54442D18(F64))
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#define exp_1 (0x4005BF0A8B145769(F64)) //The number "e"
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#define log2_10 (0x400A934F0979A371(F64))
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#define log2_e (0x3FF71547652B82FE(F64))
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#define log10_2 (0x3FD34413509F79FF(F64))
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#define loge_2 (0x3FE62E42FEFA39EF(F64))
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#define sqrt2 (0x3FF6A09E667F3BCD(F64))
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#define eps (0x3CB0000000000000(F64))
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#help_index "Data Types/Simple"
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/*CosmiC union structure is treated as a
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whole if no member is specified,
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similar to bit fields.
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//CosmiC union structure is treated as a whole if no member is specified, similar to bit fields.
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//See $LK,"::/Demo/SubIntAccess.CC"$.
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See $LK,"::/Demo/SubIntAccess.CC"$.
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*/
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U16i union U16
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{
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I8i i8[2];
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U8i u8[2];
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I8i i8[2];
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U8i u8[2];
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};
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I16i union I16
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{
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I8i i8[2];
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U8i u8[2];
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I8i i8[2];
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U8i u8[2];
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};
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U32i union U32
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{
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I8i i8[4];
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U8i u8[4];
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I16 i16[2];
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U16 u16[2];
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I8i i8[4];
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U8i u8[4];
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I16 i16[2];
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U16 u16[2];
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};
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I32i union I32
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{
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I8i i8[4];
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U8i u8[4];
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I16 i16[2];
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U16 u16[2];
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I8i i8[4];
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U8i u8[4];
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I16 i16[2];
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U16 u16[2];
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};
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U64i union U64
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{
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I8i i8[8];
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U8i u8[8];
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I16 i16[4];
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U16 u16[4];
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I32 i32[2];
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U32 u32[2];
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I8i i8[8];
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U8i u8[8];
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I16 i16[4];
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U16 u16[4];
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I32 i32[2];
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U32 u32[2];
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};
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I64i union I64
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{
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I8i i8[8];
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U8i u8[8];
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I16 i16[4];
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U16 u16[4];
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I32 i32[2];
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U32 u32[2];
|
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I8i i8[8];
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U8i u8[8];
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I16 i16[4];
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U16 u16[4];
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I32 i32[2];
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U32 u32[2];
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};
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#help_index "Math/Complex;Data Types/Complex"
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public class Complex
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{
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F64 x,y;
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F64 x, y;
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};
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#help_index "Data Types/Circular Queue"
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public class CQueue
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{
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CQueue *next,*last;
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CQueue *next, *last;
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};
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|
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#help_index "Graphics/Data Types/D3I32;Math/Data Types/D3I32;Data Types/D3I32"
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public class CD3I32 //Three dimensional I32 pt
|
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{
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I32 x,y,z;
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I32 x, y, z;
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};
|
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public class CQueueD3I32 //Queue of three dimensional I32 pts
|
||||
{
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CQueueD3I32 *next,*last;
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CD3I32 p;
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||||
CQueueD3I32 *next, *last;
|
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CD3I32 p;
|
||||
};
|
||||
#help_index "Math/Data Types;Data Types"
|
||||
public class CD2I32 //Two dimensional I32 pt
|
||||
{
|
||||
I32 x,y;
|
||||
I32 x, y;
|
||||
};
|
||||
public class CD2I64 //Two dimensional I64 pt
|
||||
{
|
||||
I64 x,y;
|
||||
I64 x, y;
|
||||
};
|
||||
public class CD3I64 //Three dimensional I64 pt
|
||||
{
|
||||
I64 x,y,z;
|
||||
I64 x, y, z;
|
||||
};
|
||||
public class CD2 //Two dimensional F64 pt
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||||
{
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||||
F64 x,y;
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||||
F64 x, y;
|
||||
};
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||||
|
||||
#help_index "Math/CD3;Data Types/CD3"
|
||||
public class CD3 //Three dimensional F64 pt
|
||||
{
|
||||
F64 x,y,z;
|
||||
F64 x, y, z;
|
||||
};
|
||||
|
||||
#help_index "Data Types/Queue Vector"
|
||||
#define QUE_VECT_U8_COUNT 512
|
||||
#define QUE_VECT_U8_COUNT 512
|
||||
public class CQueueVectU8
|
||||
{
|
||||
CQueueVectU8 *next,*last;
|
||||
I64 total_count,node_count,min_idx;
|
||||
U8 body[QUE_VECT_U8_COUNT];
|
||||
CQueueVectU8 *next,
|
||||
*last;
|
||||
I64 total_count,
|
||||
node_count,
|
||||
min_idx;
|
||||
U8 body[QUE_VECT_U8_COUNT];
|
||||
};
|
||||
|
||||
#help_index "Data Types/Fifo"
|
||||
public class CFifoU8
|
||||
{
|
||||
U8 *buf;
|
||||
I64 mask,in_ptr,out_ptr;
|
||||
U8 *buf;
|
||||
I64 mask,
|
||||
in_ptr,
|
||||
out_ptr;
|
||||
};
|
||||
public class CFifoI64
|
||||
{
|
||||
I64 *buf;
|
||||
I64 mask,in_ptr,out_ptr;
|
||||
I64 *buf,
|
||||
mask,
|
||||
in_ptr,
|
||||
out_ptr;
|
||||
};
|
||||
#help_index "Date/CMOS"
|
||||
#define CMOS_SEL 0x70 //select which reg to access using this port
|
||||
#define CMOS_DATA 0x71 //read from or write to reg using this port
|
||||
#define CMOS_SEL 0x70 //select which reg to access using this port
|
||||
#define CMOS_DATA 0x71 //read from or write to reg using this port
|
||||
|
||||
//CMOS registers
|
||||
#define CMOSR_SEC 0x0
|
||||
#define CMOSR_MIN 0x2
|
||||
#define CMOSR_HOUR 0x4
|
||||
#define CMOSR_DAY_OF_WEEK 0x6
|
||||
#define CMOSR_DAY_OF_MONTH 0x7
|
||||
#define CMOSR_MONTH 0x8
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||||
#define CMOSR_YEAR 0x9
|
||||
#define CMOSR_STATUS_A 0xA
|
||||
#define CMOSR_STATUS_B 0xB
|
||||
#define CMOSR_SEC 0x0
|
||||
#define CMOSR_MIN 0x2
|
||||
#define CMOSR_HOUR 0x4
|
||||
#define CMOSR_DAY_OF_WEEK 0x6
|
||||
#define CMOSR_DAY_OF_MONTH 0x7
|
||||
#define CMOSR_MONTH 0x8
|
||||
#define CMOSR_YEAR 0x9
|
||||
#define CMOSR_STATUS_A 0xA
|
||||
#define CMOSR_STATUS_B 0xB
|
||||
|
||||
//CMOS status flags
|
||||
#define CMOSF_BINARY (1 << 2)
|
||||
#define CMOSF_UPDATING (1 << 7)
|
||||
#define CMOSF_UPDATING (1 << 7)
|
||||
|
||||
#help_index "Date/CDate"
|
||||
#define CDATE_YEAR_DAYS 365.24225
|
||||
#define CDATE_YEAR_DAYS_INT 36524225
|
||||
#define CDATE_YEAR_DAYS 365.24225
|
||||
#define CDATE_YEAR_DAYS_INT 36524225
|
||||
#define CDATE_BASE_DAY_OF_WEEK 0
|
||||
public I64 class CDate
|
||||
{
|
||||
U32 time;
|
||||
I32 date;
|
||||
U32 time;
|
||||
I32 date;
|
||||
};
|
||||
|
||||
#help_index "Date;Date/CDate"
|
||||
public class CDateStruct
|
||||
{
|
||||
U8 sec10000,sec100,sec,min,hour,
|
||||
day_of_week,day_of_mon,mon;
|
||||
I32 year;
|
||||
U8 sec10000,
|
||||
sec100,
|
||||
sec,
|
||||
min,
|
||||
hour,
|
||||
day_of_week,
|
||||
day_of_mon,
|
||||
mon;
|
||||
I32 year;
|
||||
};
|
||||
|
||||
#help_index "Math/ODE"
|
||||
public class COrder2D3
|
||||
{
|
||||
F64 x,y,z,
|
||||
DxDt,DyDt,DzDt;
|
||||
F64 x, y, z,
|
||||
DxDt, DyDt, DzDt;
|
||||
};
|
||||
|
||||
#define MSF_INACTIVE 1
|
||||
#define MSF_FIXED 2
|
||||
public class CMass
|
||||
{
|
||||
CMass *next,*last;
|
||||
COrder2D3 *state, //Point to entries in $LK,"CMathODE",A="MN:CMathODE"$.state[]
|
||||
CMass *next,*last;
|
||||
COrder2D3 *state, //Point to entries in $LK,"CMathODE",A="MN:CMathODE"$.state[]
|
||||
*DstateDt; //Point to entries in $LK,"CMathODE",A="MN:CMathODE"$.DstateDt[]
|
||||
|
||||
U0 start;
|
||||
U32 flags,num;
|
||||
F64 mass,drag_profile_factor;
|
||||
U0 saved_state;
|
||||
F64 x,y,z,
|
||||
DxDt,DyDt,DzDt;
|
||||
U0 end;
|
||||
U0 start;
|
||||
U32 flags,
|
||||
num;
|
||||
F64 mass,
|
||||
drag_profile_factor;
|
||||
U0 saved_state;
|
||||
F64 x,y,z,
|
||||
DxDt,DyDt,DzDt;
|
||||
U0 end;
|
||||
};
|
||||
|
||||
#define SSF_INACTIVE 1
|
||||
@ -484,57 +496,47 @@ class CPatchTableAbsAddr
|
||||
#define IET_ZEROED_DATA_HEAP 24 //Not really used
|
||||
#define IET_MAIN 25
|
||||
|
||||
|
||||
#help_index "Graphics/VBE"
|
||||
|
||||
#define BLACK32 0x000000
|
||||
#define WHITE32 0xFFFFFF
|
||||
|
||||
#define VBE_MODES_NUM 32
|
||||
|
||||
class CVBEInfo
|
||||
{
|
||||
U8 signature[4];
|
||||
|
||||
U16 version;
|
||||
|
||||
U32 oem,
|
||||
capabilities,
|
||||
video_modes;
|
||||
|
||||
U16 total_memory,
|
||||
software_revision;
|
||||
|
||||
U32 vendor,
|
||||
product_name,
|
||||
product_revision;
|
||||
|
||||
U8 reserved[222],
|
||||
oem_data[256];
|
||||
U8 signature[4];
|
||||
U16 version;
|
||||
U32 oem,
|
||||
capabilities,
|
||||
video_modes;
|
||||
U16 total_memory,
|
||||
software_revision;
|
||||
U32 vendor,
|
||||
product_name,
|
||||
product_revision;
|
||||
U8 reserved[222],
|
||||
oem_data[256];
|
||||
};
|
||||
#assert sizeof(CVBEInfo)==512
|
||||
#assert sizeof(CVBEInfo) == 512
|
||||
|
||||
class CVBEMode
|
||||
{
|
||||
U16 attributes,
|
||||
pad[7],
|
||||
pitch,
|
||||
width,
|
||||
height;
|
||||
|
||||
U8 pad[3],
|
||||
bpp,
|
||||
pad,
|
||||
memory_model,
|
||||
pad[12];
|
||||
|
||||
U32 framebuffer;
|
||||
|
||||
U16 pad[9];
|
||||
|
||||
U32 max_pixel_clock;
|
||||
|
||||
U8 reserved[190];
|
||||
U16 attributes,
|
||||
pad[7],
|
||||
pitch,
|
||||
width,
|
||||
height;
|
||||
U8 pad[3],
|
||||
bpp,
|
||||
pad,
|
||||
memory_model,
|
||||
pad[12];
|
||||
U32 framebuffer;
|
||||
U16 pad[9];
|
||||
U32 max_pixel_clock;
|
||||
U8 reserved[190];
|
||||
};
|
||||
#assert sizeof(CVBEMode)==256
|
||||
#assert sizeof(CVBEMode) == 256
|
||||
|
||||
class CVBEModeShort
|
||||
{
|
||||
@ -572,106 +574,107 @@ class CKernel
|
||||
};
|
||||
|
||||
//Run-Levels
|
||||
#define RLf_16BIT 0
|
||||
#define RLf_VESA 1
|
||||
#define RLf_32BIT 2
|
||||
#define RLf_PATCHED 3
|
||||
#define RLf_16MEG_SYS_CODE_BP 4
|
||||
#define RLf_64BIT 5
|
||||
#define RLf_16MEG_ZENITH_HEAP_CTRL 6
|
||||
#define RLf_FULL_HEAPS 7
|
||||
#define RLf_RAW 8
|
||||
#define RLf_INTERRUPTS 9
|
||||
#define RLf_BLKDEV 10
|
||||
#define RLf_MP 11
|
||||
#define RLf_COMPILER 12
|
||||
#define RLf_DOC 13
|
||||
#define RLf_WINMGR 14
|
||||
#define RLf_REGISTRY 15
|
||||
#define RLf_HOME 16
|
||||
#define RLf_AUTOCOMPLETE 17
|
||||
#define RLf_16BIT 0
|
||||
#define RLf_VESA 1
|
||||
#define RLf_32BIT 2
|
||||
#define RLf_PATCHED 3
|
||||
#define RLf_16MEG_SYS_CODE_BP 4
|
||||
#define RLf_64BIT 5
|
||||
#define RLf_16MEG_ZENITH_HEAP_CTRL 6
|
||||
#define RLf_FULL_HEAPS 7
|
||||
#define RLf_RAW 8
|
||||
#define RLf_INTERRUPTS 9
|
||||
#define RLf_BLKDEV 10
|
||||
#define RLf_MP 11
|
||||
#define RLf_COMPILER 12
|
||||
#define RLf_DOC 13
|
||||
#define RLf_WINMGR 14
|
||||
#define RLf_REGISTRY 15
|
||||
#define RLf_HOME 16
|
||||
#define RLf_AUTOCOMPLETE 17
|
||||
#define RLf_ZENITH_SERVER 18
|
||||
#define RLf_ONCE_ZENITH 19
|
||||
#define RLf_ONCE_USER 20
|
||||
#define RLf_ONCE_ZENITH 19
|
||||
#define RLf_ONCE_USER 20
|
||||
|
||||
#define RLF_16BIT (1<<RLf_16BIT)
|
||||
#define RLF_VESA (1<<RLf_VESA)
|
||||
#define RLF_32BIT (1<<RLf_32BIT)
|
||||
#define RLF_PATCHED (1<<RLf_PATCHED)
|
||||
#define RLF_16MEG_SYS_CODE_BP (1<<RLf_16MEG_SYS_CODE_BP)
|
||||
#define RLF_64BIT (1<<RLf_64BIT)
|
||||
#define RLF_16MEG_ZENITH_HEAP_CTRL (1<<RLf_16MEG_ZENITH_HEAP_CTRL)
|
||||
#define RLF_FULL_HEAPS (1<<RLf_FULL_HEAPS)
|
||||
#define RLF_RAW (1<<RLf_RAW)
|
||||
#define RLF_INTERRUPTS (1<<RLf_INTERRUPTS)
|
||||
#define RLF_BLKDEV (1<<RLf_BLKDEV)
|
||||
#define RLF_MP (1<<RLf_MP)
|
||||
#define RLF_COMPILER (1<<RLf_COMPILER)
|
||||
#define RLF_DOC (1<<RLf_DOC)
|
||||
#define RLF_WINMGR (1<<RLf_WINMGR)
|
||||
#define RLF_REGISTRY (1<<RLf_REGISTRY)
|
||||
#define RLF_HOME (1<<RLf_HOME)
|
||||
#define RLF_AUTOCOMPLETE (1<<RLf_AUTOCOMPLETE)
|
||||
#define RLF_16BIT (1<<RLf_16BIT)
|
||||
#define RLF_VESA (1<<RLf_VESA)
|
||||
#define RLF_32BIT (1<<RLf_32BIT)
|
||||
#define RLF_PATCHED (1<<RLf_PATCHED)
|
||||
#define RLF_16MEG_SYS_CODE_BP (1<<RLf_16MEG_SYS_CODE_BP)
|
||||
#define RLF_64BIT (1<<RLf_64BIT)
|
||||
#define RLF_16MEG_ZENITH_HEAP_CTRL (1<<RLf_16MEG_ZENITH_HEAP_CTRL)
|
||||
#define RLF_FULL_HEAPS (1<<RLf_FULL_HEAPS)
|
||||
#define RLF_RAW (1<<RLf_RAW)
|
||||
#define RLF_INTERRUPTS (1<<RLf_INTERRUPTS)
|
||||
#define RLF_BLKDEV (1<<RLf_BLKDEV)
|
||||
#define RLF_MP (1<<RLf_MP)
|
||||
#define RLF_COMPILER (1<<RLf_COMPILER)
|
||||
#define RLF_DOC (1<<RLf_DOC)
|
||||
#define RLF_WINMGR (1<<RLf_WINMGR)
|
||||
#define RLF_REGISTRY (1<<RLf_REGISTRY)
|
||||
#define RLF_HOME (1<<RLf_HOME)
|
||||
#define RLF_AUTOCOMPLETE (1<<RLf_AUTOCOMPLETE)
|
||||
#define RLF_ZENITH_SERVER (1<<RLf_ZENITH_SERVER)
|
||||
#define RLF_ONCE_ZENITH (1<<RLf_ONCE_ZENITH)
|
||||
#define RLF_ONCE_USER (1<<RLf_ONCE_USER)
|
||||
#define RLF_ONCE_ZENITH (1<<RLf_ONCE_ZENITH)
|
||||
#define RLF_ONCE_USER (1<<RLf_ONCE_USER)
|
||||
|
||||
#help_index "Processor"
|
||||
|
||||
//Model specific regs.
|
||||
#define IA32F_SCE 0x001
|
||||
#define IA32F_LME 0x100
|
||||
#define IA32F_SCE 0x001
|
||||
#define IA32F_LME 0x100
|
||||
#define IA32_LAPIC_BASE 0x01B
|
||||
#define IA32_EFER 0xC0000080
|
||||
#define IA32_FS_BASE 0xC0000100
|
||||
#define IA32_GS_BASE 0xC0000101
|
||||
#define IA32_EFER 0xC0000080
|
||||
#define IA32_FS_BASE 0xC0000100
|
||||
#define IA32_GS_BASE 0xC0000101
|
||||
|
||||
//Programmable Interrupt Controller
|
||||
#define PIC_1 0x20
|
||||
#define PIC_1_DATA 0x21
|
||||
#define PIC_2 0xA0
|
||||
#define PIC_2_DATA 0xA1
|
||||
#define PIC_EOI 0x20 //End of interrupt
|
||||
#define PIC_1 0x20
|
||||
#define PIC_1_DATA 0x21
|
||||
#define PIC_2 0xA0
|
||||
#define PIC_2_DATA 0xA1
|
||||
#define PIC_INIT 0x11
|
||||
#define PIC_EOI 0x20 //End of interrupt
|
||||
|
||||
//Local Advanced Programmable Interrupt Controller
|
||||
#define LAPIC_BASE 0xFEE00000
|
||||
#define LAPIC_APIC_ID (LAPIC_BASE+0x020)
|
||||
#define LAPIC_BASE 0xFEE00000
|
||||
#define LAPIC_APIC_ID (LAPIC_BASE+0x020)
|
||||
#define LAPIC_APIC_VERSION (LAPIC_BASE+0x030)
|
||||
#define LAPIC_TASK_PRIORITY (LAPIC_BASE+0x080)
|
||||
#define LAPIC_ARIBITRATION_PRIORITY (LAPIC_BASE+0x090)
|
||||
#define LAPIC_PROCESSOR_PRIORITY (LAPIC_BASE+0x0A0)
|
||||
#define LAPIC_EOI (LAPIC_BASE+0x0B0)
|
||||
#define LAPIC_LOG_DST (LAPIC_BASE+0x0D0)
|
||||
#define LAPIC_DFR (LAPIC_BASE+0x0E0)
|
||||
#define LAPIC_LDR (LAPIC_BASE+0x0D0)
|
||||
#define LAPIC_ARBITRATION_PRIORITY (LAPIC_BASE+0x090)
|
||||
#define LAPIC_PROCESSOR_PRIORITY (LAPIC_BASE+0x0A0)
|
||||
#define LAPIC_EOI (LAPIC_BASE+0x0B0)
|
||||
#define LAPIC_LOG_DST (LAPIC_BASE+0x0D0)
|
||||
#define LAPIC_DFR (LAPIC_BASE+0x0E0)
|
||||
#define LAPIC_LDR (LAPIC_BASE+0x0D0)
|
||||
|
||||
#define LAPICF_APIC_ENABLED 0x100
|
||||
#define LAPIC_SVR (LAPIC_BASE+0x0F0)
|
||||
#define LAPIC_SVR (LAPIC_BASE+0x0F0)
|
||||
|
||||
#define LAPIC_ISR (LAPIC_BASE+0x100)
|
||||
#define LAPIC_TMR (LAPIC_BASE+0x180)
|
||||
#define LAPIC_IRR (LAPIC_BASE+0x200)
|
||||
#define LAPIC_ICR_LOW (LAPIC_BASE+0x300)
|
||||
#define LAPIC_ICR_HIGH (LAPIC_BASE+0x310)
|
||||
#define LAPIC_ISR (LAPIC_BASE+0x100)
|
||||
#define LAPIC_TMR (LAPIC_BASE+0x180)
|
||||
#define LAPIC_IRR (LAPIC_BASE+0x200)
|
||||
#define LAPIC_ICR_LOW (LAPIC_BASE+0x300)
|
||||
#define LAPIC_ICR_HIGH (LAPIC_BASE+0x310)
|
||||
|
||||
#define LAPIC_LVT_TIMER (LAPIC_BASE+0x320)
|
||||
#define LAPIC_LVT_TIMER (LAPIC_BASE+0x320)
|
||||
#define LAPIC_LVT_THERMAL (LAPIC_BASE+0x330)
|
||||
#define LAPIC_LVT_PERF (LAPIC_BASE+0x340)
|
||||
#define LAPIC_LVT_LINT0 (LAPIC_BASE+0x350)
|
||||
#define LAPIC_LVT_LINT1 (LAPIC_BASE+0x360)
|
||||
#define LAPIC_LVT_ERR (LAPIC_BASE+0x370)
|
||||
#define LAPIC_LVT_PERF (LAPIC_BASE+0x340)
|
||||
#define LAPIC_LVT_LINT0 (LAPIC_BASE+0x350)
|
||||
#define LAPIC_LVT_LINT1 (LAPIC_BASE+0x360)
|
||||
#define LAPIC_LVT_ERR (LAPIC_BASE+0x370)
|
||||
|
||||
#define MPN_VECT 0x97
|
||||
#define MP_VECT_ADDR (MPN_VECT*0x1000)
|
||||
#define MPN_VECT 0x97
|
||||
#define MP_VECT_ADDR (MPN_VECT*0x1000)
|
||||
|
||||
//I/O APIC Memory mapped window
|
||||
#define IOAPIC_REG 0xFEC00000 //U8
|
||||
#define IOAPIC_DATA 0xFEC00010 //U32
|
||||
#define IOAPIC_REG 0xFEC00000 //U8
|
||||
#define IOAPIC_DATA 0xFEC00010 //U32
|
||||
//I/O APIC Regs
|
||||
#define IOAPICID 0x00
|
||||
#define IOAPICVER 0x01
|
||||
#define IOAPICARB 0x02
|
||||
#define IOREDTAB 0x10
|
||||
#define IOAPICID 0x00
|
||||
#define IOAPICVER 0x01
|
||||
#define IOAPICARB 0x02
|
||||
#define IOREDTAB 0x10
|
||||
|
||||
class CAP16BitInit
|
||||
{//AP Multicore
|
||||
@ -684,13 +687,13 @@ class CAP16BitInit
|
||||
//Programmable Interval Timer
|
||||
#define PIT_0 0x40
|
||||
#define PIT_2 0x42
|
||||
#define PIT_CMD 0x43
|
||||
#define PIT_CMD 0x43
|
||||
|
||||
#define PIT_CMDF_OPMODE_RATE_GEN 0x04
|
||||
#define PIT_CMDF_OPMODE_SQUARE_WAVE 0x06
|
||||
#define PIT_CMDF_ACCESS_WORD 0x30
|
||||
#define PIT_CMDF_CHANNEL0 0x00
|
||||
#define PIT_CMDF_CHANNEL2 0x80
|
||||
#define PIT_CMDF_OPMODE_RATE_GEN 0x04
|
||||
#define PIT_CMDF_OPMODE_SQUARE_WAVE 0x06
|
||||
#define PIT_CMDF_ACCESS_WORD 0x30
|
||||
#define PIT_CMDF_CHANNEL0 0x00
|
||||
#define PIT_CMDF_CHANNEL2 0x80
|
||||
|
||||
public class CCountsGlobals
|
||||
{
|
||||
@ -702,10 +705,10 @@ public class CCountsGlobals
|
||||
Bool time_stamp_calibrated;
|
||||
};
|
||||
|
||||
#define JIFFY_FREQ 1000 // Hz
|
||||
#define CDATE_FREQ 49710 // Hz
|
||||
#define SYS_TIMER_FREQ (18333*65536/1000) //Hz
|
||||
#define SYS_TIMER0_PERIOD (65536*182/10/JIFFY_FREQ)
|
||||
#define JIFFY_FREQ 1000 // Hz
|
||||
#define CDATE_FREQ 49710 // Hz
|
||||
#define SYS_TIMER_FREQ (18333*65536/1000) //Hz
|
||||
#define SYS_TIMER0_PERIOD (65536*182/10/JIFFY_FREQ)
|
||||
|
||||
#help_index "Call"
|
||||
//Function Stack Frame
|
||||
@ -2721,15 +2724,15 @@ public class CATARep
|
||||
|
||||
#define AHCI_CAPSEXTf_BOH 0
|
||||
|
||||
#define AHCI_BOHCf_BOS 0
|
||||
#define AHCI_BOHCf_OOS 1
|
||||
#define AHCI_BOHCf_BB 4
|
||||
#define AHCI_BOHCf_BOS 0
|
||||
#define AHCI_BOHCf_OOS 1
|
||||
#define AHCI_BOHCf_BB 4
|
||||
|
||||
#define AHCI_CHDESCf_W 6
|
||||
#define AHCI_CHDESCf_W (1 << 6)
|
||||
#define AHCI_CHDESCf_W 6
|
||||
#define AHCI_CHDESCf_W (1 << 6)
|
||||
|
||||
#define AHCI_CFDESCf_C 7
|
||||
#define AHCI_CFDESCf_C (1 << 7)
|
||||
#define AHCI_CFDESCf_C 7
|
||||
#define AHCI_CFDESCf_C (1 << 7)
|
||||
|
||||
#define AHCI_PxCMDf_ST 0
|
||||
#define AHCI_PxCMDf_SUD 1
|
||||
@ -3446,21 +3449,16 @@ public I64 class CBGR48
|
||||
public class CKbdStateGlobals
|
||||
{
|
||||
I64 scan_code, //See $LK,"scan codes",A="FI:::/Doc/CharOverview.DD"$
|
||||
last_down_scan_code,
|
||||
count, //Count of keys pressed since boot.
|
||||
timestamp, //Output: TSCGet when event.
|
||||
new_key_timestamp; //Output: TSCGet when new key event.
|
||||
CFifoU8 *fifo,*fifo2; //Private
|
||||
last_down_scan_code,
|
||||
count, //Count of keys pressed since boot.
|
||||
timestamp, //Output: TSCGet when event.
|
||||
new_key_timestamp; //Output: TSCGet when new key event.
|
||||
CFifoU8 *fifo,*fifo2; //Private
|
||||
CFifoI64 *scan_code_fifo;
|
||||
|
||||
//BitTest, $LK,"Bt",A="MN:Bt"$(), with a merged scan code.
|
||||
//(Left and right shift merged, for example.)
|
||||
U32 down_bitmap[8],
|
||||
//BitTest, $LK,"Bt",A="MN:Bt"$(), with an unmerged scan code.
|
||||
down_bitmap2[8];
|
||||
|
||||
Bool reset, //Private: Reset KbdMouse
|
||||
irqs_working; //Private
|
||||
U32 down_bitmap[8], //BitTest, $LK,"Bt",A="MN:Bt"$(), with a merged scan code. (Left and right shift merged, for example.)
|
||||
down_bitmap2[8]; //BitTest, $LK,"Bt",A="MN:Bt"$(), with an unmerged scan code.
|
||||
Bool reset, //Private: Reset KbdMouse
|
||||
irqs_working; //Private
|
||||
};
|
||||
|
||||
#help_index "Mouse"
|
||||
|
Loading…
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Reference in New Issue
Block a user