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Replace harcoded masks with arg define masks

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This commit is contained in:
v0x3l 2020-03-03 18:04:51 -06:00
parent fa2e657452
commit c957c3e723
3 changed files with 13 additions and 23 deletions
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BIN
Zenith-latest-2020-03-02-17_34_27.iso → Zenith-latest-2020-03-03-18_03_35.iso
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20
src/Compiler/Asm.CC
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@ -273,30 +273,30 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
else if (arg->num.i <= U8_MAX) else if (arg->num.i <= U8_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGG_UIMM;//0xFEE; res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGG_UIMM;//0xFEE;
else if (arg->num.i <= I16_MAX) else if (arg->num.i <= I16_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 |ARGT_IMM16 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xEEE; res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xEEE;
else if (arg->num.i <= U16_MAX) else if (arg->num.i <= U16_MAX)
res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xECE; res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xECE;
else if (arg->num.i <= I32_MAX) else if (arg->num.i <= I32_MAX)
res &= 0xCCE; res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32;//0xCCE;
else if (arg->num.i <= U32_MAX) else if (arg->num.i <= U32_MAX)
res &= 0xC8E; res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64 | ARGT_UIMM32;//0xC8E;
else else
res &= 0x88E; res &= ARGG_REL | ARGT_IMM64 | ARGT_UIMM64;//0x88E;
} }
} }
else else
{ {
res &= 0x3F00FFF000; res &= ARGG_R | ARGG_RM | ARGG_M | ARGT_AL | ARGT_AX | ARGT_EAX | ARGT_RAX | ARGT_CL | ARGT_DX;//0x3F00FFF000;
if (!arg->indirect) //M8-M64 if (!arg->indirect) //M8-M64
res &= 0xFFFF0FFFFF; res &= ~ARGG_M;
} }
switch (arg->reg1) switch (arg->reg1)
{ {
case REG_RAX: res&=~0x3000000000; break; case REG_RAX: res &= ~(ARGT_CL|ARGT_DX); break;//0x3000000000;
case REG_RCX: res&=~0x2F00000000; break; case REG_RCX: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_DX); break;//~0x2F00000000
case REG_RDX: res&=~0x1F00000000; break; case REG_RDX: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_CL); break;//~0x1F00000000
default: res&=~0x3F00000000; default: res &= ~(ARGT_RAX|ARGT_EAX|ARGT_AX|ARGT_AL|ARGT_CL|ARGT_DX);//~0x3F00000000
} }
mm_done: mm_done:
return res; return res;

16
src/Home/PCNet.CC
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@ -117,18 +117,13 @@ CPCIDev* PCNetPCIDevFind()
} }
U32 PCNetGetIOBase() U32 PCNetGetIOBase()
{/* Return memory IO base address {//Return memory IO base address of PCNet card. Bits 0-4 are not for the IO base, so an AND with ~0x1F ignores those bits.
of PCNet card. Bits 0-4 are not
for the IO base, so an AND with
~0x1F ignores those bits. */
U32 io_base = pcnet.pci->base[0] & ~0x1F; U32 io_base = pcnet.pci->base[0] & ~0x1F;
return io_base; return io_base;
} }
U0 PCNetReset() U0 PCNetReset()
{/* Reads the 32- and 16-bit RESET registers, {//Reads the 32-/16-bit RESET registers, which, regardless of which mode the card is in, will reset it back to 16-bit mode.
which, regardless of which mode the card is in,
will reset it back to 16-bit mode. */
InU32(PCNetGetIOBase() + PCNET_DW_RESET); InU32(PCNetGetIOBase() + PCNET_DW_RESET);
InU16(PCNetGetIOBase() + PCNET_WD_RESET); InU16(PCNetGetIOBase() + PCNET_WD_RESET);
Sleep(1); // OSDev says minimum 1 æS Sleep(1); // OSDev says minimum 1 æS
@ -136,9 +131,7 @@ U0 PCNetReset()
U0 PCNetEnter32BitMode() U0 PCNetEnter32BitMode()
{/* AMD PCNet datasheet p. 1-930 {/* AMD PCNet datasheet p. 1-930
Summary: A 32-bit write (while in 16-bit mode) Summary: A 32-bit write (while in 16-bit mode) to RDP will cause 16-bit mode exit and immediate enter into 32-bit mode.*/
to RDP will cause 16-bit mode exit
and immediate enter into 32-bit mode. */
OutU32(PCNetGetIOBase() + PCNET_DW_RDP, 0); OutU32(PCNetGetIOBase() + PCNET_DW_RDP, 0);
} }
@ -535,9 +528,6 @@ U0 PCNetInit()
"pcnet->tx_de_buffer: %X\n",pcnet.tx_de_buffer; "pcnet->tx_de_buffer: %X\n",pcnet.tx_de_buffer;
"pcnet->rx_de_buffer_phys: %X\n",pcnet.rx_de_buffer_phys; "pcnet->rx_de_buffer_phys: %X\n",pcnet.rx_de_buffer_phys;
"pcnet->rx_de_buffer_phys: %X\n",pcnet.tx_de_buffer_phys; "pcnet->rx_de_buffer_phys: %X\n",pcnet.tx_de_buffer_phys;
} }
PCNetInit(); PCNetInit();