mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2025-06-07 08:14:48 +00:00
Add PCNet driver by TomAwezome
This commit is contained in:
v0x3l
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@ -221,7 +221,7 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
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res = comp.size_arg_mask[arg->size];
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if (aotc->seg_size == 64)
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res &= ~ARGG_MOFFS; //0xFF0FFFFFFF;
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res &= ~ARGG_MOFFS;
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if (arg->reg1 != REG_NONE && arg->imm_or_off_present && !arg->num.i &&
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!arg->num.global_asm_undef_hash && !arg->num.local_asm_undef_hash)
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@ -229,53 +229,53 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
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if (arg->reg2 != REG_NONE || arg->scale != 1)
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{//if reg or scale
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res &= ARGG_M|ARGG_RM; //0x0000FF0000;
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res &= ARGG_M|ARGG_RM;
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goto mm_done;
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}
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if (arg->indirect)
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{
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if (arg->imm_or_off_present)
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res &= ARGG_RM|ARGG_M|ARGG_MN|ARGG_MOFFS;//0x00FFFF0000;
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res &= ARGG_RM | ARGG_M | ARGG_MN | ARGG_MOFFS;
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else
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res &= ARGG_RM|ARGG_M|ARGG_MN;//0x000FFF0000;
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res &= ARGG_RM | ARGG_M | ARGG_MN;
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}
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else
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{
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if (arg->imm_or_off_present)
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res &= ARGG_MN|ARGG_IMM|ARGG_UIMM|ARGG_REL; //0x000F000FFE;
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res &= ARGG_MN | ARGG_IMM | ARGG_UIMM | ARGG_REL;
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else
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res &= ARGG_R|ARGG_RM|ARGG_M|ARGG_MN|ARGT_AL|ARGT_AX|ARGT_EAX|ARGT_RAX|ARGT_CL|ARGT_DX;//0x3F0FFFF000;
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res &= ARGG_R | ARGG_RM | ARGG_M | ARGG_MN | ARGT_AL | ARGT_AX | ARGT_EAX | ARGT_RAX | ARGT_CL | ARGT_DX;
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}
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if (arg->seg != REG_NONE)
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res &= ARGG_RM|ARGG_M|ARGG_MN|ARGG_MOFFS;//0x00FFFF0000;
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res &= ARGG_RM | ARGG_M | ARGG_MN | ARGG_MOFFS;
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if (arg->reg1 == REG_NONE)
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{
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if (arg->indirect)
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res &= ARGG_RM|ARGG_M|ARGG_MN|ARGG_MOFFS; //0x00FFFF0000;
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res &= ARGG_RM | ARGG_M | ARGG_MN | ARGG_MOFFS;
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else if (arg->num.i < 0)
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{
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if (arg->num.i >= I8_MIN)
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res &= 0x8FE;
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res &= ARGG_REL | ARGG_IMM;//|ARGT_UIMM64; //0x8FE;
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else if (arg->num.i >= I16_MIN)
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res &= 0x8EE;
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res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16;///|ARGT_UIMM64;//0x8EE;
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else if (arg->num.i >= I32_MIN)
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res &= 0x8CE;
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res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32;//|ARGT_UIMM64;//0x8CE;
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else
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res &= 0x88E;
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res &= ARGG_REL | ARGT_IMM64;//|ARGT_UIMM64;//0x88E;
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}
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else
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{
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if (arg->num.i <= I8_MAX)
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res &= 0xFFE;
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res &= ARGG_REL|ARGG_IMM|ARGG_UIMM;//0xFFE;
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else if (arg->num.i <= U8_MAX)
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res &= 0xFEE;
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res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_IMM16 | ARGG_UIMM;//0xFEE;
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else if (arg->num.i <= I16_MAX)
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res &= 0xEEE;
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res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 |ARGT_IMM16 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xEEE;
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else if (arg->num.i <= U16_MAX)
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res &= 0xECE;
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res &= ARGG_REL | ARGT_IMM64 | ARGT_IMM32 | ARGT_UIMM64 | ARGT_UIMM32 | ARGT_UIMM16;//0xECE;
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else if (arg->num.i <= I32_MAX)
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res &= 0xCCE;
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else if (arg->num.i <= U32_MAX)
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@ -283,16 +283,20 @@ I64 AsmMakeArgMask(CCompCtrl *cc, CAsmArg *arg)
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else
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res &= 0x88E;
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}
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} else {
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res&= 0x3F00FFF000;
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if (!arg->indirect) //M8-M64
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res&=0xFFFF0FFFFF;
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}
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switch (arg->reg1) {
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else
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{
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res &= 0x3F00FFF000;
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if (!arg->indirect) //M8-M64
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res &= 0xFFFF0FFFFF;
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}
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switch (arg->reg1)
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{
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case REG_RAX: res&=~0x3000000000; break;
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case REG_RCX: res&=~0x2F00000000; break;
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case REG_RDX: res&=~0x1F00000000; break;
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default: res&=~0x3F00000000;
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default: res&=~0x3F00000000;
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}
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mm_done:
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return res;
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543
src/Home/PCNet.CC
Executable file
543
src/Home/PCNet.CC
Executable file
@ -0,0 +1,543 @@
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/* AMD PCNetII Driver
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Author: TomAwezome
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Driver is based on:
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- minexew's ShrineOS PCNet.CC implementation
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- OSDev AMD_PCNET documentation
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- AMD PCnet(TM)-PCI datasheet
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- any other useful sources.
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Guidelines:
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- Magic numbers are bad. #defines are good.
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- Understandability over LOC.
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- Clear documentation.
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*/
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#define PCNET_DEVICE_ID 0x2000
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#define PCNET_VENDOR_ID 0x1022
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#define PCI_REG_COMMAND 0x04
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#define PCNET_CMDf_IOEN 0
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#define PCNET_CMDf_BMEN 2
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#define PCNET_CMDF_IOEN (1 << PCNET_CMDf_IOEN)
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#define PCNET_CMDF_BMEN (1 << PCNET_CMDf_BMEN)
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#define PCNET_WD_RESET 0x14 // reset reg location when card is in 16-bit mode
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#define PCNET_DW_RDP 0x10
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#define PCNET_DW_RAP 0x14
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#define PCNET_DW_RESET 0x18 // reset reg location when card is in 32-bit mode
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#define PCNET_CSR_CTRLSTATUS 0
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#define PCNET_CSR_INTERRUPTS 3
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#define PCNET_CSR_FEATURECTRL 4
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#define PCNET_CSR_LADRF0 8
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#define PCNET_CSR_LADRF1 9
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#define PCNET_CSR_LADRF2 10
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#define PCNET_CSR_LADRF3 11
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#define PCNET_CSR_PADR0 12
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#define PCNET_CSR_PADR1 13
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#define PCNET_CSR_PADR2 14
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#define PCNET_CSR_MODE 15
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#define PCNET_CSR_BADRL 24
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#define PCNET_CSR_BADRU 25
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#define PCNET_CSR_BADTL 30
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#define PCNET_CSR_BADTU 31
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#define PCNET_CSR_POLLINT 47
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#define PCNET_CSR_SOFTWARESTYLE 58
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#define PCNET_CSR_RXRINGLEN 76
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#define PCNET_CSR_TXRINGLEN 78
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#define PCNET_SWSTYLE_SELECTION 2 // AMD PCNet datasheet p. 1-968
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// Refer to AMD PCNet datasheet p. 1-954, 1-956, 1-957 for Interrupt Mask details.
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#define PCNET_INT_BSWP 2 // Byte Swap (Big-Endian / Little-Endian)
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#define PCNET_INT_IDONM 8 // Initialization Done Mask
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#define PCNET_INT_TINTM 9 // Transmit Interrupt Mask
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#define PCNET_INT_RINTM 10 // Receive Interrupt Mask
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#define PCNET_FEATURE_APADXMT 11
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#define PCNET_CTRL_INIT 0
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#define PCNET_CTRL_STRT 1
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#define PCNET_CTRL_STOP 2
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#define PCNET_CTRL_RINT 10
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#define PCNET_RX_BUFF_COUNT 32 // Linux & Shrine Driver use 32 and 8 for
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#define PCNET_TX_BUFF_COUNT 8 // these, we could allow more if wanted.
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#define PCNET_DESCRIPTORf_OWN 31 // AMD PCNet datasheet p.1-992, 1-994
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//#define PCNET_DESCRIPTORF_OWN (1 << PCNET_DESCRIPTORf_OWN)
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/* Ethernet Frame Size. Linux uses 1544,
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OSDev and Shrine use 1548. Based on
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IEEE 802.3as, max frame size was agreed
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upon as 2000 bytes. */
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#define ETHERNET_FRAME_SIZE 2000
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#define INT_DEST_CPU 0
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class CPCNet
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{
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CPCIDev* pci;
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U8 mac_address[6]; //MAC address is first 6 bytes of PCNet EEPROM (page # ? )
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I64 current_rx_de_index; // Current Receive DE being processed. Gets incremented, wrapped to 0 at max of PCNET_RX_BUFF_COUNT.
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I64 current_tx_de_index; // Current Transmit DE being processed. Gets incremented, wrapped to 0 at max of PCNET_TX_BUFF_COUNT.
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U8* rx_de_buffer; // Uncached-alias of pointer to the buffer of RX Descriptor Entries.
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U8* tx_de_buffer; // Uncached-alias of pointer to the buffer of TX Descriptor Entries.
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U8* rx_de_buffer_phys; // Pointer to the buffer of RX Descriptor Entries. (Code Heap, lower 2Gb)
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U8* tx_de_buffer_phys; // Pointer to the buffer of TX Descriptor Entries. (Code Heap, lower 2Gb)
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U32 rx_buffer_addr; // 'Physical address of actual receive buffers (< 4 Gb)'
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U32 tx_buffer_addr; // 'Physical address of actual transmit buffers (< 4 Gb)'
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} pcnet; // pcnet is the global variable we store all of this into.
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class CPCNetDescriptorEntry
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{/* AMD PCNet datasheet p.1-991 & p.1-994 NOTE: chart typo on 1-994, see ONES and BCNT on 1-995.
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TX and RX DE's are the same size (16-Bytes) and structure,
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but have different registers and functions.
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The RX and TX DE buffers of the CPCNet class
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are allocated to a certain amount of these DEs. */
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U32 buffer_addr;
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U32 status1;
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U32 status2;
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U32 reserved;
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};
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CPCIDev* PCNetPCIDevFind()
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{// Find and return PCNetII card as a CPCIDev pointer.
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return PCIDevFind(,,PCNET_VENDOR_ID,PCNET_DEVICE_ID);
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}
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U32 PCNetGetIOBase()
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{/* Return memory IO base address
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of PCNet card. Bits 0-4 are not
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for the IO base, so an AND with
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~0x1F ignores those bits. */
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U32 io_base = pcnet.pci->base[0] & ~0x1F;
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return io_base;
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}
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U0 PCNetReset()
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{/* Reads the 32- and 16-bit RESET registers,
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which, regardless of which mode the card is in,
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will reset it back to 16-bit mode. */
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InU32(PCNetGetIOBase() + PCNET_DW_RESET);
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InU16(PCNetGetIOBase() + PCNET_WD_RESET);
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Sleep(1); // OSDev says minimum 1 æS
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}
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U0 PCNetEnter32BitMode()
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{/* AMD PCNet datasheet p. 1-930
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Summary: A 32-bit write (while in 16-bit mode)
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to RDP will cause 16-bit mode exit
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and immediate enter into 32-bit mode. */
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OutU32(PCNetGetIOBase() + PCNET_DW_RDP, 0);
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}
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U0 PCNetWriteRAP(U32 value)
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{/* AMD PCNet datasheet p. 1-952
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Summary: Register Address Pointer register
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value will indicate which CSR / BCR register
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we want to access in RDP / BDP. */
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OutU32(PCNetGetIOBase() + PCNET_DW_RAP, value);
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}
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U0 PCNetWriteCSR(U32 csr, U32 value)
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{/* AMD PCNet datasheet p. 1-952
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Summary: Control and Status Registers are
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accessed via the RDP (Register Data Port).
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Which CSR is selected is based on the value
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in the RAP. */
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PCNetWriteRAP(csr);
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OutU32(PCNetGetIOBase() + PCNET_DW_RDP, value);
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}
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U32 PCNetReadCSR(U32 csr)
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{/* AMD PCNet datasheet p. 1-952
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Summary: Control and Status Registers are
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accessed via the RDP (Register Data Port).
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Which CSR is selected is based on the value
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in the RAP. */
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PCNetWriteRAP(csr);
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return InU32(PCNetGetIOBase() + PCNET_DW_RDP);
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}
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U0 PCNetSetSWStyle()
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{/* AMD PCNet datasheet p. 1-968
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In CSR58 (Software Style), the 8-bit
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SWSTYLE register dictates interpretation of certain
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bits in the CSR space, and widths of descriptors and
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initialization block. In PCINet-PCI mode, CSR4 bits
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function as defined in the datasheet , and TMD1[29]
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functions as ADD_FCS. */
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U32 csr = PCNetReadCSR(PCNET_CSR_SOFTWARESTYLE);
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csr &= ~0xFF; // clears first 8 bits: SWSTYLE 8-bit register.
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csr |= PCNET_SWSTYLE_SELECTION; // set SWSTYLE to PCNet-PCI mode.
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PCNetWriteCSR(PCNET_CSR_SOFTWARESTYLE, csr);
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}
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U0 PCNetGetMAC()
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{/* AMD PCNet datasheet p. 1-887, 1-931, 1-937
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MAC address stored at first 6 bytes of PCNet EEPROM.
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EEPROM addresses shadow-copied to APROM at hardware init.
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APROM accessible at first 16 bytes of PCI IO space. */
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I64 i;
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for (i = 0; i < 6; i++)
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{
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pcnet.mac_address[i] = InU8(PCNetGetIOBase() + i);
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}
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}
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U0 PCNetInitDescriptorEntry(CPCNetDescriptorEntry* entry, U32 buffer_address, I64 is_rx)
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{
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entry->buffer_addr = buffer_address;
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/* AMD PCNet datasheet p.1-991.
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BCNT is the usable buffer length, expressed as first
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12 bits of 2s-complement of desired length.
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Bits 0-11 of a DE are for the buffer byte count (BCNT),
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and bits 12-15 of a DE must be written all ones (ONES) */
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U16 buffer_byte_count = -ETHERNET_FRAME_SIZE; // Sets up as 2s complement of the desired length.
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buffer_byte_count &= 0x0FFF; // Masks 0 over everything except bits 0-11.
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entry->status1 |= buffer_byte_count; // Sets BCNT reg (first 12 bits) in DE TMD1/RMD1.
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entry->status1 |= 0xF000; // Sets bits 12-15 (ONES) in DE TMD1/RMD1 as all ones.
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//if this is a Receive DE, give ownership to the card so the PCNet can fill them.
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if (is_rx)
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Bts(&entry->status1, PCNET_DESCRIPTORf_OWN);
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ClassRep(entry);
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}
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U0 PCNetAllocateBuffers()
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{
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I64 de_index; // used in for loops for TX and RX DE access.
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/* AMD PCNet datasheet p.1-913, p.1-990
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When SSIZE32=1, Descriptor Ring Entry Base Address
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must be on 16-byte boundary. (TDRA[3:0]=0, RDRA[3:0]=0) */
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pcnet.rx_de_buffer_phys = CAllocAligned(sizeof(CPCNetDescriptorEntry) * PCNET_RX_BUFF_COUNT,
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16,
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Fs->code_heap);
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pcnet.tx_de_buffer_phys = CAllocAligned(sizeof(CPCNetDescriptorEntry) * PCNET_TX_BUFF_COUNT,
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16,
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Fs->code_heap);
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//Shrine does a check and returns -1 here, if the end of either buffer exceeds 0x100000000
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pcnet.rx_de_buffer = dev.uncached_alias + pcnet.rx_de_buffer_phys; // we want uncached
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pcnet.tx_de_buffer = dev.uncached_alias + pcnet.tx_de_buffer_phys; // access to these.
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pcnet.rx_buffer_addr = CAlloc(ETHERNET_FRAME_SIZE * PCNET_RX_BUFF_COUNT, //Shrine has a TODO to figure out
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Fs->code_heap);
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pcnet.tx_buffer_addr = CAlloc(ETHERNET_FRAME_SIZE * PCNET_TX_BUFF_COUNT, //if these should be uncached too.
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Fs->code_heap); //note, p.1-991,1-994: RBADR is only 32 bits wide.
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//Shrine does a check and returns -1 here, if the end of either buffer exceeds 0x100000000
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CPCNetDescriptorEntry* entry;
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entry = pcnet.rx_de_buffer;
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for (de_index = 0; de_index < PCNET_RX_BUFF_COUNT; de_index++)
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{
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PCNetInitDescriptorEntry(&entry[de_index], pcnet.rx_buffer_addr, TRUE); // TRUE for is_rx.
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}
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entry = pcnet.tx_de_buffer;
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for (de_index = 0; de_index < PCNET_TX_BUFF_COUNT; de_index++)
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{
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PCNetInitDescriptorEntry(&entry[de_index], pcnet.tx_buffer_addr, FALSE); // FALSE for is_rx.
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}
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}
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U0 PCNetDirectInit()
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{/* AMD PCNet datasheet p. 1-1021
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Instead of setting up initialization block,
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direct writes to the necessary CSRs can be
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used to manually initialize the PCNet card. */
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/* AMD PCNet datasheet p.1-991
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If Logical Address Filter is set as
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all 0, all incoming logical addresses
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are rejected. Disables multicast. */
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PCNetWriteCSR(PCNET_CSR_LADRF0, 0);
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PCNetWriteCSR(PCNET_CSR_LADRF1, 0);
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PCNetWriteCSR(PCNET_CSR_LADRF2, 0);
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PCNetWriteCSR(PCNET_CSR_LADRF3, 0);
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/* The Physical Address is the MAC.
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AMD PCNet datasheet p.1-960, 1-961
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The first 16 bits of CSRs 12-14 are
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for the Physical Address, the upper bits
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are reserved, written 0 read undefined.
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The OR and bit-shift of 8 allows writing
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separate U8 values in the correct locations
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of the CSR. */
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PCNetWriteCSR(PCNET_CSR_PADR0,
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pcnet.mac_address[0] | (pcnet.mac_address[1] << 8));
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PCNetWriteCSR(PCNET_CSR_PADR1,
|
||||
pcnet.mac_address[2] | (pcnet.mac_address[3] << 8));
|
||||
PCNetWriteCSR(PCNET_CSR_PADR2,
|
||||
pcnet.mac_address[4] | (pcnet.mac_address[5] << 8));
|
||||
|
||||
/* AMD PCNet datasheet p.1-961, 1-962, 1-963
|
||||
Refer to datasheet for specifics.
|
||||
Most relevant, when setting Mode to 0,
|
||||
promiscuous mode is is disabled, TX and
|
||||
RX enabled, enable RX broadcast and unicast. */
|
||||
PCNetWriteCSR(PCNET_CSR_MODE, 0);
|
||||
|
||||
/* AMD PCNet datasheet p.1-964
|
||||
CSR 24 and 25 need to be filled
|
||||
with the lower and upper 16 bits,
|
||||
respectively, of the address of
|
||||
the RX packet ring. Likewise for
|
||||
CSR 30 and 31 for the TX packet ring.
|
||||
|
||||
0xFFFF AND on address will leave
|
||||
only lower 16 bits remaining.
|
||||
|
||||
Bitshift right of 16 will replace
|
||||
first 16 bits with upper 16 bits,
|
||||
remaining bits cleared.*/
|
||||
PCNetWriteCSR(PCNET_CSR_BADRL,
|
||||
pcnet.rx_buffer_addr & 0xFFFF);
|
||||
PCNetWriteCSR(PCNET_CSR_BADRU,
|
||||
pcnet.rx_buffer_addr >> 16);
|
||||
|
||||
PCNetWriteCSR(PCNET_CSR_BADTL,
|
||||
pcnet.tx_buffer_addr & 0xFFFF);
|
||||
PCNetWriteCSR(PCNET_CSR_BADTU,
|
||||
pcnet.tx_buffer_addr >> 16);
|
||||
|
||||
/* AMD PCNet datasheet p. 1-967
|
||||
Default value at hardware init is
|
||||
all 0. Standard init block process
|
||||
sets this, but if doing directly
|
||||
it is imperative to manually set it 0. */
|
||||
PCNetWriteCSR(PCNET_CSR_POLLINT, 0);
|
||||
|
||||
/* AMD PCNet datasheet p. 1-970
|
||||
Receive and Transmit Ring Length CSRs
|
||||
bits 0-15 need to be set as the 2s complement
|
||||
of the ring length. The AND with 0xFFFF clears
|
||||
the upper Reserved bits, which are to be written
|
||||
as zeroes read undefined. */
|
||||
PCNetWriteCSR(PCNET_CSR_RXRINGLEN,
|
||||
-PCNET_RX_BUFF_COUNT & 0xFFFF);
|
||||
PCNetWriteCSR(PCNET_CSR_TXRINGLEN,
|
||||
-PCNET_TX_BUFF_COUNT & 0xFFFF);
|
||||
|
||||
|
||||
}
|
||||
|
||||
U0 PCNetSetInterruptCSR()
|
||||
{/* AMD PCNet datasheet p.1-952, 1-953, 1-954, 1-955, 1-956, 1-957
|
||||
Refer to datasheet for specifics on the Interrupt Masks.
|
||||
Most of these, when set 0, allow interrupts to be set in CSR0.
|
||||
We set Big-Endian disabled, RX interrupts
|
||||
enabled, Init Done interrupt disabled, and TX interrupt
|
||||
disabled. */
|
||||
U32 csr = PCNetReadCSR(PCNET_CSR_INTERRUPTS);
|
||||
|
||||
Btr(&csr, PCNET_INT_BSWP);
|
||||
Btr(&csr, PCNET_INT_RINTM);
|
||||
|
||||
Bts(&csr, PCNET_INT_IDONM);
|
||||
Bts(&csr, PCNET_INT_TINTM);
|
||||
|
||||
PCNetWriteCSR(PCNET_CSR_INTERRUPTS, csr);
|
||||
}
|
||||
|
||||
U0 PCNetEnableTXAutoPad()
|
||||
{/* AMD PCNet datasheet p.1-958
|
||||
Setting bit 11 (Auto Pad Transmit) allows
|
||||
shoft transmit frames to be automatically
|
||||
extended to 64 bytes. */
|
||||
U32 csr = PCNetReadCSR(PCNET_CSR_FEATURECTRL);
|
||||
|
||||
Bts(&csr, PCNET_FEATURE_APADXMT);
|
||||
|
||||
PCNetWriteCSR(PCNET_CSR_FEATURECTRL, csr);
|
||||
|
||||
}
|
||||
|
||||
U0 PCNetExitConfigMode()
|
||||
{/* AMD PCNet datasheet p.1-954
|
||||
PCNet controller can be started
|
||||
after configuring by ensuring INIT
|
||||
and STOP are cleared and START bit
|
||||
is set, in Status and Control Register
|
||||
(CSR0). */
|
||||
U32 csr = PCNetReadCSR(PCNET_CSR_CTRLSTATUS);
|
||||
|
||||
Btr(&csr, PCNET_CTRL_INIT);
|
||||
Btr(&csr, PCNET_CTRL_STOP);
|
||||
|
||||
Bts(&csr, PCNET_CTRL_STRT);
|
||||
|
||||
}
|
||||
|
||||
I64 PCNetDriverOwns(CPCNetDescriptorEntry* entry)
|
||||
{/* Returns whether the value of the OWN bit of the
|
||||
Descriptor Entry is zero. If 0, driver owns,
|
||||
if 1, PCNet card owns it. */
|
||||
return !Bt(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
|
||||
}
|
||||
|
||||
I64 PCNetReceivePacket(U8** packet_buffer_out, U16* packet_length_out)
|
||||
{/* Receives the packet at the current RX DE index. Parameters
|
||||
are both pointers, since we modify the value at the packet_buffer_out,
|
||||
and at the packet_length, ending with returning the index of the DE
|
||||
we just processed.
|
||||
The MCNT is stored at the first two bytes of the RMD2. We AND with
|
||||
0xFFFF to only take in those first two bytes: that is the packet_length.
|
||||
The increment of the current RX DE index is done by assigning it the
|
||||
value of incrementing it AND the max DE index-1. This will increment it
|
||||
as well as wrap back to 0 if we hit the max DE index. */
|
||||
I64 de_index = pcnet.current_rx_de_index;
|
||||
|
||||
CPCNetDescriptorEntry* entry = pcnet.rx_de_buffer;
|
||||
entry = &entry[de_index];
|
||||
|
||||
U16 packet_length = entry->status2 & 0xFFFF;
|
||||
|
||||
pcnet.current_rx_de_index = (pcnet.current_rx_de_index + 1)
|
||||
& (PCNET_RX_BUFF_COUNT - 1);
|
||||
|
||||
|
||||
*packet_buffer_out = pcnet.rx_buffer_addr + (de_index * ETHERNET_FRAME_SIZE);
|
||||
*packet_length_out = packet_length;
|
||||
return de_index;
|
||||
|
||||
|
||||
}
|
||||
|
||||
U0 PCNetReleaseReceivePacket(I64 de_index)
|
||||
{/* Release ownership of the packet to the PCNet card
|
||||
by setting the OWN bit to 1. */
|
||||
CPCNetDescriptorEntry* entry = pcnet.rx_de_buffer;
|
||||
entry = &entry[de_index];
|
||||
|
||||
Bts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
}
|
||||
|
||||
interrupt U0 PCNetIRQ()
|
||||
{// todo: comments explaining proces...maybe reimplement interrupt handling altogether.
|
||||
U32 csr = PCNetReadCSR(PCNET_CSR_CTRLSTATUS);
|
||||
//"Interrupt Reason: %X , %b\n",csr,csr;
|
||||
|
||||
CPCNetDescriptorEntry* entry = pcnet.rx_de_buffer;
|
||||
|
||||
while (PCNetDriverOwns(&entry[pcnet.current_rx_de_index]))
|
||||
{
|
||||
U8* packet_buffer;
|
||||
U16 packet_length;
|
||||
I64 de_index = PCNetReceivePacket(packet_buffer, packet_length);
|
||||
|
||||
if (de_index >= 0) // necessary? check increment logic in PCNetReceivePacket.
|
||||
{
|
||||
//NetFIFOPushCopy(packet_buffer, packet_length);
|
||||
PCNetReleaseReceivePacket(de_index);
|
||||
}
|
||||
|
||||
Bts(&csr, PCNET_CTRL_RINT);
|
||||
|
||||
PCNetWriteCSR(PCNET_CSR_CTRLSTATUS, csr);
|
||||
}
|
||||
|
||||
*(dev.uncached_alias + LAPIC_EOI)(U32*) = 0;
|
||||
}
|
||||
|
||||
U0 PCIRerouteInterrupts(I64 base)
|
||||
{ // todo: comments explaining process, maybe better var names
|
||||
I64 i;
|
||||
U8* da = dev.uncached_alias + IOAPIC_REG;
|
||||
U32* _d = dev.uncached_alias + IOAPIC_DATA;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
*da = IOREDTAB + i*2 + 1;
|
||||
*_d = dev.mp_apic_ids[INT_DEST_CPU] << 24;
|
||||
*da = IOREDTAB + i*2;
|
||||
*_d = 0x4000 + base + i;
|
||||
}
|
||||
}
|
||||
|
||||
U0 PCNetSetupInterrupts()
|
||||
{ // todo: comments explaining process
|
||||
IntEntrySet(I_USER+0, &PCNetIRQ, IDTET_IRQ);
|
||||
IntEntrySet(I_USER+1, &PCNetIRQ, IDTET_IRQ);
|
||||
IntEntrySet(I_USER+2, &PCNetIRQ, IDTET_IRQ);
|
||||
IntEntrySet(I_USER+3, &PCNetIRQ, IDTET_IRQ);
|
||||
PCIRerouteInterrupts(I_USER);
|
||||
}
|
||||
|
||||
U0 PCNetInit()
|
||||
{
|
||||
MemSet(&pcnet, 0, sizeof(CPCNet)); // pcnet global var will hold member data the driver uses often.
|
||||
|
||||
pcnet.pci = PCNetPCIDevFind();
|
||||
if (pcnet.pci == NULL)
|
||||
return; // if we don't find the card, quit.
|
||||
|
||||
/* Clear command register of PCNet
|
||||
PCI device, set IO Enable and Bus
|
||||
Master Enable bits of the register. */
|
||||
PCIWriteU16(pcnet.pci->bus,
|
||||
pcnet.pci->dev,
|
||||
pcnet.pci->fun,
|
||||
PCI_REG_COMMAND,
|
||||
PCNET_CMDF_IOEN | PCNET_CMDF_BMEN);
|
||||
|
||||
PCNetReset();
|
||||
|
||||
PCNetEnter32BitMode();
|
||||
|
||||
PCNetSetSWStyle();
|
||||
|
||||
PCNetGetMAC();
|
||||
// OSDev has code ensuring auto selected connection...
|
||||
|
||||
PCNetAllocateBuffers();
|
||||
|
||||
PCNetDirectInit();
|
||||
|
||||
PCNetSetInterruptCSR();
|
||||
|
||||
PCNetEnableTXAutoPad();
|
||||
|
||||
PCNetExitConfigMode();
|
||||
|
||||
PCNetSetupInterrupts();
|
||||
|
||||
|
||||
Sleep(100);//? necssary?
|
||||
ClassRep(&pcnet);
|
||||
|
||||
"pcnet->rx_de_buffer: %X\n",pcnet.rx_de_buffer;
|
||||
"pcnet->tx_de_buffer: %X\n",pcnet.tx_de_buffer;
|
||||
"pcnet->rx_de_buffer_phys: %X\n",pcnet.rx_de_buffer_phys;
|
||||
"pcnet->rx_de_buffer_phys: %X\n",pcnet.tx_de_buffer_phys;
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
PCNetInit();
|
||||
10
src/Home/Registry.CC
Executable file
10
src/Home/Registry.CC
Executable file
@ -0,0 +1,10 @@
|
||||
$TR,"Zenith"$
|
||||
$ID,2$$TR,"SysMessageFlags"$
|
||||
$ID,2$sys_message_flags[0]=0;
|
||||
$ID,-2$$TR,"SysRegVer"$
|
||||
$ID,2$registry_version=1.000;
|
||||
$ID,-2$$ID,-2$$TR,"Once"$
|
||||
$ID,2$$TR,"Zenith"$
|
||||
$ID,2$$ID,-2$$TR,"User"$
|
||||
$ID,2$$ID,-2$$ID,-2$$TR,"AutoComplete"$
|
||||
$ID,2$ac.col = TEXT_COLS-30;ac.row = TEXT_ROWS/5+4;$ID,-2$
|
||||
@ -52,4 +52,4 @@ U0 Tmp()
|
||||
}
|
||||
}
|
||||
Tmp;
|
||||
PaletteSetSmooth;
|
||||
PaletteSetGruvboxLight;
|
||||
Loading…
x
Reference in New Issue
Block a user